deccounter.tan.summary

基于VHDL的4位带异步清零的二进制计数器。

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.219 ns
From           : REG4B:inst2|DOUT[3]
To             : OUT1[3]
From Clock     : CLKK
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : CNT4B:inst7|CQI[3]
To             : CNT4B:inst7|CQI[3]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLKK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : TESTCTL:inst8|DIV2CLK
To             : TESTCTL:inst8|DIV2CLK
From Clock     : CLKK
To Clock       : CLKK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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