pwm_control.tan.rpt

基于VHDL的直流电机的PWM控制程序。

+--------------------------------------------------------------+
; tsu                                                          ;
+-------+--------------+------------+------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To     ; To Clock ;
+-------+--------------+------------+------+--------+----------+
; N/A   ; None         ; 6.175 ns   ; Z_F  ; z~reg0 ; clk      ;
; N/A   ; None         ; 5.532 ns   ; Z_F  ; f~reg0 ; clk      ;
+-------+--------------+------------+------+--------+----------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+---------+----------------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To             ; From Clock ;
+-------+--------------+------------+---------+----------------+------------+
; N/A   ; None         ; 11.570 ns  ; cnt4[0] ; level_display0 ; Level      ;
; N/A   ; None         ; 11.566 ns  ; cnt4[1] ; level_display1 ; Level      ;
; N/A   ; None         ; 7.980 ns   ; z~reg0  ; z              ; clk        ;
; N/A   ; None         ; 6.907 ns   ; f~reg0  ; f              ; clk        ;
+-------+--------------+------------+---------+----------------+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To     ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A           ; None        ; -5.480 ns ; Z_F  ; f~reg0 ; clk      ;
; N/A           ; None        ; -6.123 ns ; Z_F  ; z~reg0 ; clk      ;
+---------------+-------------+-----------+------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Jan 18 23:31:54 2003
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pwm_control -c pwm_control --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "Level" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "speed[0]" and destination register "agb"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.325 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y10_N1; Fanout = 1; REG Node = 'speed[0]'
            Info: 2: + IC(0.550 ns) + CELL(0.590 ns) = 1.140 ns; Loc. = LC_X22_Y10_N9; Fanout = 1; COMB Node = 'LessThan0~177'
            Info: 3: + IC(0.447 ns) + CELL(0.738 ns) = 2.325 ns; Loc. = LC_X22_Y10_N2; Fanout = 2; REG Node = 'agb'
            Info: Total cell delay = 1.328 ns ( 57.12 % )
            Info: Total interconnect delay = 0.997 ns ( 42.88 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.782 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 10; CLK Node = 'clk'
                Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X22_Y10_N2; Fanout = 2; REG Node = 'agb'
                Info: Total cell delay = 2.180 ns ( 78.36 % )
                Info: Total interconnect delay = 0.602 ns ( 21.64 % )
            Info: - Longest clock path from clock "clk" to source register is 2.782 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 10; CLK Node = 'clk'
                Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X22_Y10_N1; Fanout = 1; REG Node = 'speed[0]'
                Info: Total cell delay = 2.180 ns ( 78.36 % )
                Info: Total interconnect delay = 0.602 ns ( 21.64 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock "Level" Internal fmax is restricted to 275.03 MHz between source register "cnt4[0]" and destination register "cnt4[1]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.841 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y9_N5; Fanout = 6; REG Node = 'cnt4[0]'
            Info: 2: + IC(0.532 ns) + CELL(0.309 ns) = 0.841 ns; Loc. = LC_X22_Y9_N2; Fanout = 5; REG Node = 'cnt4[1]'
            Info: Total cell delay = 0.309 ns ( 36.74 % )
            Info: Total interconnect delay = 0.532 ns ( 63.26 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "Level" to destination register is 7.297 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 2; CLK Node = 'Level'
                Info: 2: + IC(5.117 ns) + CELL(0.711 ns) = 7.297 ns; Loc. = LC_X22_Y9_N2; Fanout = 5; REG Node = 'cnt4[1]'
                Info: Total cell delay = 2.180 ns ( 29.88 % )
                Info: Total interconnect delay = 5.117 ns ( 70.12 % )
            Info: - Longest clock path from clock "Level" to source register is 7.297 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 2; CLK Node = 'Level'
                Info: 2: + IC(5.117 ns) + CELL(0.711 ns) = 7.297 ns; Loc. = LC_X22_Y9_N5; Fanout = 6; REG Node = 'cnt4[0]'
                Info: Total cell delay = 2.180 ns ( 29.88 % )
                Info: Total interconnect delay = 5.117 ns ( 70.12 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "z~reg0" (data pin = "Z_F", clock pin = "clk") is 6.175 ns
    Info: + Longest pin to register delay is 8.920 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 2; PIN Node = 'Z_F'
        Info: 2: + IC(7.142 ns) + CELL(0.309 ns) = 8.920 ns; Loc. = LC_X22_Y10_N4; Fanout = 1; REG Node = 'z~reg0'
        Info: Total cell delay = 1.778 ns ( 19.93 % )
        Info: Total interconnect delay = 7.142 ns ( 80.07 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X22_Y10_N4; Fanout = 1; REG Node = 'z~reg0'
        Info: Total cell delay = 2.180 ns ( 78.36 % )
        Info: Total interconnect delay = 0.602 ns ( 21.64 % )
Info: tco from clock "Level" to destination pin "level_display0" through register "cnt4[0]" is 11.570 ns
    Info: + Longest clock path from clock "Level" to source register is 7.297 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 2; CLK Node = 'Level'
        Info: 2: + IC(5.117 ns) + CELL(0.711 ns) = 7.297 ns; Loc. = LC_X22_Y9_N5; Fanout = 6; REG Node = 'cnt4[0]'
        Info: Total cell delay = 2.180 ns ( 29.88 % )
        Info: Total interconnect delay = 5.117 ns ( 70.12 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.049 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y9_N5; Fanout = 6; REG Node = 'cnt4[0]'
        Info: 2: + IC(1.925 ns) + CELL(2.124 ns) = 4.049 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'level_display0'
        Info: Total cell delay = 2.124 ns ( 52.46 % )
        Info: Total interconnect delay = 1.925 ns ( 47.54 % )
Info: th for register "f~reg0" (data pin = "Z_F", clock pin = "clk") is -5.480 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.768 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X12_Y10_N2; Fanout = 1; REG Node = 'f~reg0'
        Info: Total cell delay = 2.180 ns ( 78.76 % )
        Info: Total interconnect delay = 0.588 ns ( 21.24 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 8.263 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 2; PIN Node = 'Z_F'
        Info: 2: + IC(6.056 ns) + CELL(0.738 ns) = 8.263 ns; Loc. = LC_X12_Y10_N2; Fanout = 1; REG Node = 'f~reg0'
        Info: Total cell delay = 2.207 ns ( 26.71 % )
        Info: Total interconnect delay = 6.056 ns ( 73.29 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 106 megabytes of memory during processing
    Info: Processing ended: Sat Jan 18 23:31:57 2003
    Info: Elapsed time: 00:00:03