pwm_control.tan.qmsg

基于VHDL的直流电机的PWM控制程序。

{ "Info" "ITDB_TH_RESULT" "f~reg0 Z_F clk -5.480 ns register " "Info: th for register \"f~reg0\" (data pin = \"Z_F\", clock pin = \"clk\") is -5.480 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.768 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.711 ns) 2.768 ns f~reg0 2 REG LC_X12_Y10_N2 1 " "Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X12_Y10_N2; Fanout = 1; REG Node = 'f~reg0'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { clk f~reg0 } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 65 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.76 % ) " "Info: Total cell delay = 2.180 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.588 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.588 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk f~reg0 } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk clk~out0 f~reg0 } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 65 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.263 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.263 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Z_F 1 PIN PIN_3 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 2; PIN Node = 'Z_F'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Z_F } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.056 ns) + CELL(0.738 ns) 8.263 ns f~reg0 2 REG LC_X12_Y10_N2 1 " "Info: 2: + IC(6.056 ns) + CELL(0.738 ns) = 8.263 ns; Loc. = LC_X12_Y10_N2; Fanout = 1; REG Node = 'f~reg0'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.794 ns" { Z_F f~reg0 } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 65 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 26.71 % ) " "Info: Total cell delay = 2.207 ns ( 26.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.056 ns ( 73.29 % ) " "Info: Total interconnect delay = 6.056 ns ( 73.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.263 ns" { Z_F f~reg0 } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "8.263 ns" { Z_F Z_F~out0 f~reg0 } { 0.000ns 0.000ns 6.056ns } { 0.000ns 1.469ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk f~reg0 } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk clk~out0 f~reg0 } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.263 ns" { Z_F f~reg0 } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "8.263 ns" { Z_F Z_F~out0 f~reg0 } { 0.000ns 0.000ns 6.056ns } { 0.000ns 1.469ns 0.738ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 18 23:31:57 2003 " "Info: Processing ended: Sat Jan 18 23:31:57 2003" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}