pwm_control.tan.qmsg

基于VHDL的直流电机的PWM控制程序。

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register speed\[0\] agb 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"speed\[0\]\" and destination register \"agb\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.325 ns + Longest register register " "Info: + Longest register to register delay is 2.325 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns speed\[0\] 1 REG LC_X22_Y10_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y10_N1; Fanout = 1; REG Node = 'speed\[0\]'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { speed[0] } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.590 ns) 1.140 ns LessThan0~177 2 COMB LC_X22_Y10_N9 1 " "Info: 2: + IC(0.550 ns) + CELL(0.590 ns) = 1.140 ns; Loc. = LC_X22_Y10_N9; Fanout = 1; COMB Node = 'LessThan0~177'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.140 ns" { speed[0] LessThan0~177 } "NODE_NAME" } } { "d:/alter/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.447 ns) + CELL(0.738 ns) 2.325 ns agb 3 REG LC_X22_Y10_N2 2 " "Info: 3: + IC(0.447 ns) + CELL(0.738 ns) = 2.325 ns; Loc. = LC_X22_Y10_N2; Fanout = 2; REG Node = 'agb'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.185 ns" { LessThan0~177 agb } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.328 ns ( 57.12 % ) " "Info: Total cell delay = 1.328 ns ( 57.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 42.88 % ) " "Info: Total interconnect delay = 0.997 ns ( 42.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.325 ns" { speed[0] LessThan0~177 agb } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "2.325 ns" { speed[0] LessThan0~177 agb } { 0.000ns 0.550ns 0.447ns } { 0.000ns 0.590ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns agb 2 REG LC_X22_Y10_N2 2 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X22_Y10_N2; Fanout = 2; REG Node = 'agb'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk agb } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk agb } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 agb } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns speed\[0\] 2 REG LC_X22_Y10_N1 1 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X22_Y10_N1; Fanout = 1; REG Node = 'speed\[0\]'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk speed[0] } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk speed[0] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 speed[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk agb } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 agb } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk speed[0] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 speed[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.325 ns" { speed[0] LessThan0~177 agb } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "2.325 ns" { speed[0] LessThan0~177 agb } { 0.000ns 0.550ns 0.447ns } { 0.000ns 0.590ns 0.738ns } "" } } { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk agb } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 agb } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk speed[0] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 speed[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { agb } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { agb } {  } {  } "" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 14 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "Level register register cnt4\[0\] cnt4\[1\] 275.03 MHz Internal " "Info: Clock \"Level\" Internal fmax is restricted to 275.03 MHz between source register \"cnt4\[0\]\" and destination register \"cnt4\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.841 ns + Longest register register " "Info: + Longest register to register delay is 0.841 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt4\[0\] 1 REG LC_X22_Y9_N5 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y9_N5; Fanout = 6; REG Node = 'cnt4\[0\]'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt4[0] } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.532 ns) + CELL(0.309 ns) 0.841 ns cnt4\[1\] 2 REG LC_X22_Y9_N2 5 " "Info: 2: + IC(0.532 ns) + CELL(0.309 ns) = 0.841 ns; Loc. = LC_X22_Y9_N2; Fanout = 5; REG Node = 'cnt4\[1\]'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.841 ns" { cnt4[0] cnt4[1] } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 36.74 % ) " "Info: Total cell delay = 0.309 ns ( 36.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.532 ns ( 63.26 % ) " "Info: Total interconnect delay = 0.532 ns ( 63.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.841 ns" { cnt4[0] cnt4[1] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "0.841 ns" { cnt4[0] cnt4[1] } { 0.000ns 0.532ns } { 0.000ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Level destination 7.297 ns + Shortest register " "Info: + Shortest clock path from clock \"Level\" to destination register is 7.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Level 1 CLK PIN_2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 2; CLK Node = 'Level'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Level } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.117 ns) + CELL(0.711 ns) 7.297 ns cnt4\[1\] 2 REG LC_X22_Y9_N2 5 " "Info: 2: + IC(5.117 ns) + CELL(0.711 ns) = 7.297 ns; Loc. = LC_X22_Y9_N2; Fanout = 5; REG Node = 'cnt4\[1\]'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.828 ns" { Level cnt4[1] } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 29.88 % ) " "Info: Total cell delay = 2.180 ns ( 29.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.117 ns ( 70.12 % ) " "Info: Total interconnect delay = 5.117 ns ( 70.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.297 ns" { Level cnt4[1] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "7.297 ns" { Level Level~out0 cnt4[1] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Level source 7.297 ns - Longest register " "Info: - Longest clock path from clock \"Level\" to source register is 7.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Level 1 CLK PIN_2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 2; CLK Node = 'Level'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Level } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.117 ns) + CELL(0.711 ns) 7.297 ns cnt4\[0\] 2 REG LC_X22_Y9_N5 6 " "Info: 2: + IC(5.117 ns) + CELL(0.711 ns) = 7.297 ns; Loc. = LC_X22_Y9_N5; Fanout = 6; REG Node = 'cnt4\[0\]'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.828 ns" { Level cnt4[0] } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 29.88 % ) " "Info: Total cell delay = 2.180 ns ( 29.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.117 ns ( 70.12 % ) " "Info: Total interconnect delay = 5.117 ns ( 70.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.297 ns" { Level cnt4[0] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "7.297 ns" { Level Level~out0 cnt4[0] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.297 ns" { Level cnt4[1] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "7.297 ns" { Level Level~out0 cnt4[1] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.297 ns" { Level cnt4[0] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "7.297 ns" { Level Level~out0 cnt4[0] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.841 ns" { cnt4[0] cnt4[1] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "0.841 ns" { cnt4[0] cnt4[1] } { 0.000ns 0.532ns } { 0.000ns 0.309ns } "" } } { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.297 ns" { Level cnt4[1] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "7.297 ns" { Level Level~out0 cnt4[1] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.297 ns" { Level cnt4[0] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "7.297 ns" { Level Level~out0 cnt4[0] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt4[1] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { cnt4[1] } {  } {  } "" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 20 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "z~reg0 Z_F clk 6.175 ns register " "Info: tsu for register \"z~reg0\" (data pin = \"Z_F\", clock pin = \"clk\") is 6.175 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.920 ns + Longest pin register " "Info: + Longest pin to register delay is 8.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Z_F 1 PIN PIN_3 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 2; PIN Node = 'Z_F'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Z_F } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.142 ns) + CELL(0.309 ns) 8.920 ns z~reg0 2 REG LC_X22_Y10_N4 1 " "Info: 2: + IC(7.142 ns) + CELL(0.309 ns) = 8.920 ns; Loc. = LC_X22_Y10_N4; Fanout = 1; REG Node = 'z~reg0'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.451 ns" { Z_F z~reg0 } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 65 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 19.93 % ) " "Info: Total cell delay = 1.778 ns ( 19.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.142 ns ( 80.07 % ) " "Info: Total interconnect delay = 7.142 ns ( 80.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.920 ns" { Z_F z~reg0 } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "8.920 ns" { Z_F Z_F~out0 z~reg0 } { 0.000ns 0.000ns 7.142ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 65 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns z~reg0 2 REG LC_X22_Y10_N4 1 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X22_Y10_N4; Fanout = 1; REG Node = 'z~reg0'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk z~reg0 } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 65 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk z~reg0 } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 z~reg0 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.920 ns" { Z_F z~reg0 } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "8.920 ns" { Z_F Z_F~out0 z~reg0 } { 0.000ns 0.000ns 7.142ns } { 0.000ns 1.469ns 0.309ns } "" } } { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk z~reg0 } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 z~reg0 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Level level_display0 cnt4\[0\] 11.570 ns register " "Info: tco from clock \"Level\" to destination pin \"level_display0\" through register \"cnt4\[0\]\" is 11.570 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Level source 7.297 ns + Longest register " "Info: + Longest clock path from clock \"Level\" to source register is 7.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Level 1 CLK PIN_2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 2; CLK Node = 'Level'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Level } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.117 ns) + CELL(0.711 ns) 7.297 ns cnt4\[0\] 2 REG LC_X22_Y9_N5 6 " "Info: 2: + IC(5.117 ns) + CELL(0.711 ns) = 7.297 ns; Loc. = LC_X22_Y9_N5; Fanout = 6; REG Node = 'cnt4\[0\]'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.828 ns" { Level cnt4[0] } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 29.88 % ) " "Info: Total cell delay = 2.180 ns ( 29.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.117 ns ( 70.12 % ) " "Info: Total interconnect delay = 5.117 ns ( 70.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.297 ns" { Level cnt4[0] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "7.297 ns" { Level Level~out0 cnt4[0] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.049 ns + Longest register pin " "Info: + Longest register to pin delay is 4.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt4\[0\] 1 REG LC_X22_Y9_N5 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y9_N5; Fanout = 6; REG Node = 'cnt4\[0\]'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt4[0] } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.925 ns) + CELL(2.124 ns) 4.049 ns level_display0 2 PIN PIN_85 0 " "Info: 2: + IC(1.925 ns) + CELL(2.124 ns) = 4.049 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'level_display0'" {  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.049 ns" { cnt4[0] level_display0 } "NODE_NAME" } } { "pwm_control.vhd" "" { Text "F:/20044934/pwm_control.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 52.46 % ) " "Info: Total cell delay = 2.124 ns ( 52.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.925 ns ( 47.54 % ) " "Info: Total interconnect delay = 1.925 ns ( 47.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.049 ns" { cnt4[0] level_display0 } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "4.049 ns" { cnt4[0] level_display0 } { 0.000ns 1.925ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.297 ns" { Level cnt4[0] } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "7.297 ns" { Level Level~out0 cnt4[0] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.049 ns" { cnt4[0] level_display0 } "NODE_NAME" } } { "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/71/quartus/bin/Technology_Viewer.qrui" "4.049 ns" { cnt4[0] level_display0 } { 0.000ns 1.925ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}