📄 pwm_control.sim.rpt
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+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+------------------+
; |PWM_CONTROL|rst ; |PWM_CONTROL|rst ; out ;
; |PWM_CONTROL|LessThan0~20 ; |PWM_CONTROL|LessThan0~20 ; out0 ;
; |PWM_CONTROL|LessThan0~21 ; |PWM_CONTROL|LessThan0~21 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[0]~0 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[0]~0 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[0] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[0] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~1 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~1 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~2 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~2 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[3]~1 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[3]~1 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[3] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[3] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[2] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[2] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[1] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[1] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~4 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~4 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~5 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~5 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~6 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~6 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~0 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|result_node[0]~0 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|result_node[0]~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~3 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~3 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~7 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~7 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~0 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|result_node[0]~0 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|result_node[0]~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~3 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~3 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~3 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~3 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~5 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~5 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|w_result19w~0 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|w_result19w~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~7 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~7 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~1 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~1 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~2 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~2 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[1]~1 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[1]~1 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~4 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~4 ; out0 ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+------------------+
; |PWM_CONTROL|rst ; |PWM_CONTROL|rst ; out ;
; |PWM_CONTROL|LessThan0~20 ; |PWM_CONTROL|LessThan0~20 ; out0 ;
; |PWM_CONTROL|LessThan0~21 ; |PWM_CONTROL|LessThan0~21 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[0]~0 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[0]~0 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[0] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[0] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~1 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~1 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~2 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~2 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[3]~1 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[3]~1 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[3] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[3] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[2] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[2] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[1] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|datab_node[1] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~4 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~4 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~5 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~5 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~6 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~6 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~0 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|result_node[0]~0 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|result_node[0]~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~3 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~3 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~7 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~7 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~0 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|result_node[0]~0 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|result_node[0]~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~3 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~3 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~3 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~3 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~5 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~5 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|w_result19w~0 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|w_result19w~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~7 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~7 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~1 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~1 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~2 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~2 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[1]~1 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[1]~1 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~4 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~4 ; out0 ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Thu Nov 29 19:46:20 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off pwm_control -c pwm_control
Info: Using vector source file "E:/20044934/pwm_control.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 76.64 %
Info: Number of transitions in simulation is 5959
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 93 megabytes of memory during processing
Info: Processing ended: Thu Nov 29 19:46:22 2007
Info: Elapsed time: 00:00:02
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