📄 pwm_control.sim.rpt
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+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------+
; |PWM_CONTROL|cnt4[1] ; |PWM_CONTROL|cnt4[1] ; regout ;
; |PWM_CONTROL|cnt4[0] ; |PWM_CONTROL|cnt4[0] ; regout ;
; |PWM_CONTROL|speed[2] ; |PWM_CONTROL|speed[2] ; regout ;
; |PWM_CONTROL|speed[1] ; |PWM_CONTROL|speed[1] ; regout ;
; |PWM_CONTROL|speed[0] ; |PWM_CONTROL|speed[0] ; regout ;
; |PWM_CONTROL|agb ; |PWM_CONTROL|agb ; regout ;
; |PWM_CONTROL|cnt16[3] ; |PWM_CONTROL|cnt16[3] ; regout ;
; |PWM_CONTROL|cnt16[2] ; |PWM_CONTROL|cnt16[2] ; regout ;
; |PWM_CONTROL|cnt16[1] ; |PWM_CONTROL|cnt16[1] ; regout ;
; |PWM_CONTROL|z~0 ; |PWM_CONTROL|z~0 ; out ;
; |PWM_CONTROL|f~0 ; |PWM_CONTROL|f~0 ; out ;
; |PWM_CONTROL|cnt16[0] ; |PWM_CONTROL|cnt16[0] ; regout ;
; |PWM_CONTROL|z~reg0 ; |PWM_CONTROL|z~reg0 ; regout ;
; |PWM_CONTROL|f~reg0 ; |PWM_CONTROL|f~reg0 ; regout ;
; |PWM_CONTROL|Level ; |PWM_CONTROL|Level ; out ;
; |PWM_CONTROL|clk ; |PWM_CONTROL|clk ; out ;
; |PWM_CONTROL|Z_F ; |PWM_CONTROL|Z_F ; out ;
; |PWM_CONTROL|z ; |PWM_CONTROL|z ; pin_out ;
; |PWM_CONTROL|f ; |PWM_CONTROL|f ; pin_out ;
; |PWM_CONTROL|level_display0 ; |PWM_CONTROL|level_display0 ; pin_out ;
; |PWM_CONTROL|level_display1 ; |PWM_CONTROL|level_display1 ; pin_out ;
; |PWM_CONTROL|LessThan0~16 ; |PWM_CONTROL|LessThan0~16 ; out0 ;
; |PWM_CONTROL|LessThan0~17 ; |PWM_CONTROL|LessThan0~17 ; out0 ;
; |PWM_CONTROL|LessThan0~18 ; |PWM_CONTROL|LessThan0~18 ; out0 ;
; |PWM_CONTROL|LessThan0~19 ; |PWM_CONTROL|LessThan0~19 ; out0 ;
; |PWM_CONTROL|LessThan0~22 ; |PWM_CONTROL|LessThan0~22 ; out0 ;
; |PWM_CONTROL|LessThan0~23 ; |PWM_CONTROL|LessThan0~23 ; out0 ;
; |PWM_CONTROL|LessThan0~24 ; |PWM_CONTROL|LessThan0~24 ; out0 ;
; |PWM_CONTROL|LessThan0~25 ; |PWM_CONTROL|LessThan0~25 ; out0 ;
; |PWM_CONTROL|LessThan0~26 ; |PWM_CONTROL|LessThan0~26 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|result_node[0] ; |PWM_CONTROL|lpm_add_sub:Add1|result_node[0] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|result_node[1] ; |PWM_CONTROL|lpm_add_sub:Add1|result_node[1] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|result_node[2] ; |PWM_CONTROL|lpm_add_sub:Add1|result_node[2] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|result_node[3] ; |PWM_CONTROL|lpm_add_sub:Add1|result_node[3] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[0]~0 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[0]~0 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[0] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[0] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~0 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~0 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~3 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~3 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3]~1 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3]~1 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[2]~2 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[2]~2 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[1]~3 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[1]~3 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[2] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[2] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[1] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|unreg_res_node[1] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~7 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~7 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~8 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~8 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~9 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~9 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~10 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~10 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~11 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~11 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~12 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~12 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~13 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~13 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~14 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~14 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~15 ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|_~15 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; sout ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[2] ; cout ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[1] ; cout ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout ;
; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |PWM_CONTROL|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~1 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~1 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~2 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~2 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|result_node[0]~1 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|result_node[0]~1 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|result_node[0] ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|result_node[0] ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~4 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~4 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~5 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~5 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~6 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|_~6 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|w_result19w~0 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|w_result19w~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|w_result19w~1 ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|w_result19w~1 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|w_result19w ; |PWM_CONTROL|lpm_mux:Mux2|mux_cfc:auto_generated|w_result19w ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~1 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~1 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~2 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~2 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|result_node[0]~1 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|result_node[0]~1 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|result_node[0] ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|result_node[0] ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~4 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~4 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~5 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~5 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~6 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~6 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|w_result19w~0 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|w_result19w~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~7 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|_~7 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|w_result19w~1 ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|w_result19w~1 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|w_result19w ; |PWM_CONTROL|lpm_mux:Mux1|mux_cfc:auto_generated|w_result19w ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~0 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~1 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~1 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|result_node[0]~0 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|result_node[0]~0 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~2 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~2 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|result_node[0]~1 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|result_node[0]~1 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|result_node[0] ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|result_node[0] ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~4 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~4 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~6 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|_~6 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|w_result19w~1 ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|w_result19w~1 ; out0 ;
; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|w_result19w ; |PWM_CONTROL|lpm_mux:Mux0|mux_cfc:auto_generated|w_result19w ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|result_node[0] ; |PWM_CONTROL|lpm_add_sub:Add0|result_node[0] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|result_node[1] ; |PWM_CONTROL|lpm_add_sub:Add0|result_node[1] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0] ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~0 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~0 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~3 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~3 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~1 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~1 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1] ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1] ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~5 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~5 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~6 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~6 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~7 ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|_~7 ; out0 ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout ;
; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |PWM_CONTROL|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout ;
+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
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