📄 ths8200_beta.c
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///////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
// This driver has been tested under the following Modes of the THS8200: //
// Standard Input Syncs Output //
// //
// ATSC 480p 20-bit Embedded YPbPr //
// ATSC 720p 20-bit Embedded YPbPr //
// ATSC 1080i 20-bit Embedded YPbPr //
///////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
#include <std.h>
#include "edc.h"
#include "_iic.h"
#include "ths8200_beta.h"
/* In daughter card 1, address selecting pin I2CA = 0 so WRITE address is 0x40 *
* and read address 0x41. */
#define THS8200_address (0x40>>1)
/* private definitions */
#define NO_CGMS 1
#define CSC_RAWDATA 2
#define CSC_BYPASS 3
#define CSM_OFF 4
#define NO_TEST 5
extern I2C_Handle EVMDM642_I2C_hI2C;
static int I2C_writeReg(Uint8 devAddr, Uint8 subAddr, Uint8 data)
{
_IIC_write(EVMDM642_I2C_hI2C, THS8200_address, subAddr, &data, 1);
return TRUE;
}
static int cgms_config(int Devid,int mode) {
int status = 1;
switch(mode) {
case NO_CGMS:
break;
default:
status &= I2C_writeReg(Devid,0x83,0x00); // cgms_header
status &= I2C_writeReg(Devid,0x84,0x00); // cgms_payload_msb
status &= I2C_writeReg(Devid,0x85,0x00); // cgms_payload_lsb
break;
}
return status;
}
static int csc_config(int Devid,int mode) {
int status = 1;
switch(mode){
case CSC_BYPASS:
status &= I2C_writeReg(Devid,0x04,0x81); // csc_ric1
status &= I2C_writeReg(Devid,0x05,0xD5); // csc_rfc1
status &= I2C_writeReg(Devid,0x06,0x00); // csc_ric2
status &= I2C_writeReg(Devid,0x07,0x00); // csc_rfc2
status &= I2C_writeReg(Devid,0x08,0x06); // csc_ric3
status &= I2C_writeReg(Devid,0x09,0x29); // csc_rfc3
status &= I2C_writeReg(Devid,0x0A,0x04); // csc_gic1
status &= I2C_writeReg(Devid,0x0B,0x00); // csc_gfc1
status &= I2C_writeReg(Devid,0x0C,0x04); // csc_gic2
status &= I2C_writeReg(Devid,0x0D,0x00); // csc_gfc2
status &= I2C_writeReg(Devid,0x0E,0x04); // csc_gic3
status &= I2C_writeReg(Devid,0x0F,0x00); // csc_gfc3
status &= I2C_writeReg(Devid,0x10,0x80); // csc_bic1
status &= I2C_writeReg(Devid,0x11,0xBB); // csc_bfc1
status &= I2C_writeReg(Devid,0x12,0x07); // csc_bic2
status &= I2C_writeReg(Devid,0x13,0x44); // csc_bfc2
status &= I2C_writeReg(Devid,0x14,0x00); // csc_bic3
status &= I2C_writeReg(Devid,0x15,0x00); // csc_bfc3
status &= I2C_writeReg(Devid,0x16,0x14); // csc_offset1
status &= I2C_writeReg(Devid,0x17,0xAE); // csc_offset12
status &= I2C_writeReg(Devid,0x18,0x8B); // csc_offset23
status &= I2C_writeReg(Devid,0x19,0x02); // csc_offset3
break;
case CSC_RAWDATA:
default:
status &= I2C_writeReg(Devid,0x04,0x00); // csc_ric1
status &= I2C_writeReg(Devid,0x05,0x00); // csc_rfc1
status &= I2C_writeReg(Devid,0x06,0x00); // csc_ric2
status &= I2C_writeReg(Devid,0x07,0x00); // csc_rfc2
status &= I2C_writeReg(Devid,0x08,0x00); // csc_ric3
status &= I2C_writeReg(Devid,0x09,0x00); // csc_rfc3
status &= I2C_writeReg(Devid,0x0A,0x00); // csc_gic1
status &= I2C_writeReg(Devid,0x0B,0x00); // csc_gfc1
status &= I2C_writeReg(Devid,0x0C,0x00); // csc_gic2
status &= I2C_writeReg(Devid,0x0D,0x00); // csc_gfc2
status &= I2C_writeReg(Devid,0x0E,0x00); // csc_gic3
status &= I2C_writeReg(Devid,0x0F,0x00); // csc_gfc3
status &= I2C_writeReg(Devid,0x10,0x00); // csc_bic1
status &= I2C_writeReg(Devid,0x11,0x00); // csc_bfc1
status &= I2C_writeReg(Devid,0x12,0x00); // csc_bic2
status &= I2C_writeReg(Devid,0x13,0x00); // csc_bfc2
status &= I2C_writeReg(Devid,0x14,0x00); // csc_bic3
status &= I2C_writeReg(Devid,0x15,0x00); // csc_bfc3
status &= I2C_writeReg(Devid,0x16,0x00); // csc_offset1
status &= I2C_writeReg(Devid,0x17,0x00); // csc_offset12
status &= I2C_writeReg(Devid,0x18,0x00); // csc_offset23
status &= I2C_writeReg(Devid,0x19,0x03); // csc_offset3
break;
}
return status;
}
static int csm_config(int Devid,int mode) {
int status = 1;
switch(mode) {
case CSM_OFF:
status &= I2C_writeReg(Devid,0x4A,0x00); // csm_mult_gy_msb
break;
default:
status &= I2C_writeReg(Devid,0x41,0x40); // csm_clip_gy_low
status &= I2C_writeReg(Devid,0x42,0x40); // csm_clip_bcb_low
status &= I2C_writeReg(Devid,0x43,0x40); // csm_clip_rcr_low
status &= I2C_writeReg(Devid,0x44,0x53); // csm_clip_gy_high
status &= I2C_writeReg(Devid,0x45,0x3F); // csm_clip_bcb_high
status &= I2C_writeReg(Devid,0x46,0x3F); // csm_clip_rcr_high
status &= I2C_writeReg(Devid,0x47,0x40); // csm_shift_gy
status &= I2C_writeReg(Devid,0x48,0x40); // csm_shift_bcb
status &= I2C_writeReg(Devid,0x49,0x40); // csm_shift_rcr
status &= I2C_writeReg(Devid,0x4A,0x08); // csm_mult_gy_msb
status &= I2C_writeReg(Devid,0x4B,0x00); // csm_mult_bcb_rcr_msb
status &= I2C_writeReg(Devid,0x4C,0x00); // csm_mult_gy_lsb
status &= I2C_writeReg(Devid,0x4D,0x00); // csm_mult_bcb_lsb
status &= I2C_writeReg(Devid,0x4E,0x00); // csm_mult_rcr_lsb
status &= I2C_writeReg(Devid,0x4F,0x00); // csm_mode
break;
}
return status;
}
static int test_config(int Devid,int mode) {
int status = 1;
switch(mode){
case NO_TEST:
default:
status &= I2C_writeReg(Devid,0x1A,0x00); // tst_cntl
status &= I2C_writeReg(Devid,0x1B,0x00); // tst_ramp_cntl
break;
}
return status;
}
static Bool THS8200_config(EDC_Handle handle, THS8200_Params *params) {
int status = 1;
int Devid = THS8200_address;
/* configure the test mode*/
status &= test_config(Devid,NO_TEST);
/* configure CSM */
status &= csm_config(Devid,CSM_OFF);
/*Configure CGMS */
status &= cgms_config(Devid,NO_CGMS);
/*configure CSC */
status &= csc_config(Devid,CSC_RAWDATA);
///////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
// THS8200 480p, 20bit YCbCr in, YPbPr out, Embedded input syncs //
///////////////////////////////////////////////////////////////////////////////////
if(params->outFmt == YPbPr_480P_HDTV) {
/*Configure the input SYNC signal,either embedded or dedicated */
if(params->inFmt == BT656_EMBEDDED_SYNC) {
status &= I2C_writeReg(Devid,0x82,0x3F); // pol_cntl
status &= I2C_writeReg(Devid,0x1C,0x04); // dman_cntl
}
else if(params->inFmt == BT656_EXTERNAL_SYNC) {
status &= I2C_writeReg(Devid,0x82,0x1F); // pol_cntl
status &= I2C_writeReg(Devid,0x1C,0x04); // dman_cntl
}
else if(params->inFmt == YCx20_EXTERNAL_SYNC) {
status &= I2C_writeReg(Devid,0x82,0x1F); // pol_cntl
status &= I2C_writeReg(Devid,0x1C,0x03); // dman_cntl
}
else if(params->inFmt == YCx20_EMBEDDED_SYNC) {
status &= I2C_writeReg(Devid,0x82,0x3F); // pol_cntl
status &= I2C_writeReg(Devid,0x1C,0x03); // dman_cntl
}
else {
return(FALSE);
}
/*configure Dispaly Time Generator,Data Manager */
status &= I2C_writeReg(Devid,0x03,0x11); // chip_ctl
status &= I2C_writeReg(Devid,0x1D,0xFF); // dtg_y_sync1
status &= I2C_writeReg(Devid,0x1E,0x49); // dtg_y_sync2
status &= I2C_writeReg(Devid,0x1F,0xFF); // dtg_y_sync3 these set up output sync levels
status &= I2C_writeReg(Devid,0x20,0xFF); // dtg_cbcr_sync1
status &= I2C_writeReg(Devid,0x21,0xFF); // dtg_cbcr_sync2
status &= I2C_writeReg(Devid,0x22,0xFF); // dtg_cbcr_sync3
status &= I2C_writeReg(Devid,0x23,0x11); // dtg_y_sync_upper
status &= I2C_writeReg(Devid,0x24,0x15); // dtg_cbcr_sync_upper
status &= I2C_writeReg(Devid,0x25,0x3D); // dtg_spec_a these spec registers set up horizontal timing parameters
status &= I2C_writeReg(Devid,0x26,0x10); // dtg_spec_b
status &= I2C_writeReg(Devid,0x27,0x20); // dtg_spec_c
status &= I2C_writeReg(Devid,0x28,0x7A); // dtg_spec_d
status &= I2C_writeReg(Devid,0x29,0x00); // dtg_spec_d1
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