arm_dpimacros.h

this program is for arm cpu and wince

/* Macros for DPI ops, auto-generated from template */


/* mov/mvn */

/* Rd := imm8 ROR rot */
#define ARM_MOV_REG_IMM_COND(p, reg, imm8, rot, cond) \
	ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_MOV, reg, 0, imm8, rot, cond)
#define ARM_MOV_REG_IMM(p, reg, imm8, rot) \
	ARM_MOV_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL)
/* S */
#define ARM_MOVS_REG_IMM_COND(p, reg, imm8, rot, cond) \
	ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_MOV, reg, 0, imm8, rot, cond)
#define ARM_MOVS_REG_IMM(p, reg, imm8, rot) \
	ARM_MOVS_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL)

#ifndef ARM_NOIASM
#define _MOV_REG_IMM_COND(reg, imm8, rot, cond) \
	ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_MOV, reg, 0, imm8, rot, cond)
#define _MOV_REG_IMM(reg, imm8, rot) \
	_MOV_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL)
/* S */
#define _MOVS_REG_IMM_COND(reg, imm8, rot, cond) \
	ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_MOV, reg, 0, imm8, rot, cond)
#define _MOVS_REG_IMM(reg, imm8, rot) \
	_MOVS_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL)
#endif


/* Rd := imm8 */
#define ARM_MOV_REG_IMM8_COND(p, reg, imm8, cond) \
	ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_MOV, reg, 0, imm8, 0, cond)
#define ARM_MOV_REG_IMM8(p, reg, imm8) \
	ARM_MOV_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL)
/* S */
#define ARM_MOVS_REG_IMM8_COND(p, reg, imm8, cond) \
	ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_MOV, reg, 0, imm8, 0, cond)
#define ARM_MOVS_REG_IMM8(p, reg, imm8) \
	ARM_MOVS_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL)

#ifndef ARM_NOIASM
#define _MOV_REG_IMM8_COND(reg, imm8, cond) \
	ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_MOV, reg, 0, imm8, 0, cond)
#define _MOV_REG_IMM8(reg, imm8) \
	_MOV_REG_IMM8_COND(reg, imm8, ARMCOND_AL)
/* S */
#define _MOVS_REG_IMM8_COND(reg, imm8, cond) \
	ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_MOV, reg, 0, imm8, 0, cond)
#define _MOVS_REG_IMM8(reg, imm8) \
	_MOVS_REG_IMM8_COND(reg, imm8, ARMCOND_AL)
#endif


/* Rd := Rm */
#define ARM_MOV_REG_REG_COND(p, rd, rm, cond) \
	ARM_DPIOP_REG_REG_COND(p, ARMOP_MOV, rd, 0, rm, cond)
#define ARM_MOV_REG_REG(p, rd, rm) \
	ARM_MOV_REG_REG_COND(p, rd, rm, ARMCOND_AL)
/* S */
#define ARM_MOVS_REG_REG_COND(p, rd, rm, cond) \
	ARM_DPIOP_S_REG_REG_COND(p, ARMOP_MOV, rd, 0, rm, cond)
#define ARM_MOVS_REG_REG(p, rd, rm) \
	ARM_MOVS_REG_REG_COND(p, rd, rm, ARMCOND_AL)

#ifndef ARM_NOIASM
#define _MOV_REG_REG_COND(rd, rm, cond) \
	ARM_IASM_DPIOP_REG_REG_COND(ARMOP_MOV, rd, 0, rm, cond)
#define _MOV_REG_REG(rd, rm) \
	_MOV_REG_REG_COND(rd, rm, ARMCOND_AL)
/* S */
#define _MOVS_REG_REG_COND(rd, rm, cond) \
	ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_MOV, rd, 0, rm, cond)
#define _MOVS_REG_REG(rd, rm) \
	_MOVS_REG_REG_COND(rd, rm, ARMCOND_AL)
#endif


/* Rd := Rm <shift_type> imm_shift */
#define ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \
	ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_MOV, rd, 0, rm, shift_type, imm_shift, cond)
#define ARM_MOV_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \
	ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL)
/* S */
#define ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \
	ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_MOV, rd, 0, rm, shift_type, imm_shift, cond)
#define ARM_MOVS_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \
	ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL)

#ifndef ARM_NOIASM
#define _MOV_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \
	ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_MOV, rd, 0, rm, shift_type, imm_shift, cond)
#define _MOV_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \
	_MOV_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL)
/* S */
#define _MOVS_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \
	ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_MOV, rd, 0, rm, shift_type, imm_shift, cond)
#define _MOVS_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \
	_MOVS_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL)
#endif



/* Rd := (Rm <shift_type> Rs) */
#define ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \
	ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_MOV, rd, 0, rm, shift_type, rs, cond)
#define ARM_MOV_REG_REGSHIFT(p, rd, rm, shift_type, rs) \
	ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL)
/* S */
#define ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \
	ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_MOV, rd, 0, rm, shift_type, rs, cond)
#define ARM_MOVS_REG_REGSHIFT(p, rd, rm, shift_type, rs) \
	ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL)

#ifndef ARM_NOIASM
#define _MOV_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \
	ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_MOV, rd, 0, rm, shift_type, rs, cond)
#define _MOV_REG_REGSHIFT(rd, rm, shift_type, rs) \
	_MOV_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL)
/* S */
#define _MOVS_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \
	ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_MOV, rd, 0, rm, shift_type, rs, cond)
#define _MOVS_REG_REGSHIFT(rd, rm, shift_type, rs) \
	_MOVS_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL)
#endif


/* Rd := imm8 ROR rot */
#define ARM_MVN_REG_IMM_COND(p, reg, imm8, rot, cond) \
	ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_MVN, reg, 0, imm8, rot, cond)
#define ARM_MVN_REG_IMM(p, reg, imm8, rot) \
	ARM_MVN_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL)
/* S */
#define ARM_MVNS_REG_IMM_COND(p, reg, imm8, rot, cond) \
	ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_MVN, reg, 0, imm8, rot, cond)
#define ARM_MVNS_REG_IMM(p, reg, imm8, rot) \
	ARM_MVNS_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL)

#ifndef ARM_NOIASM
#define _MVN_REG_IMM_COND(reg, imm8, rot, cond) \
	ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_MVN, reg, 0, imm8, rot, cond)
#define _MVN_REG_IMM(reg, imm8, rot) \
	_MVN_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL)
/* S */
#define _MVNS_REG_IMM_COND(reg, imm8, rot, cond) \
	ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_MVN, reg, 0, imm8, rot, cond)
#define _MVNS_REG_IMM(reg, imm8, rot) \
	_MVNS_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL)
#endif


/* Rd := imm8 */
#define ARM_MVN_REG_IMM8_COND(p, reg, imm8, cond) \
	ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_MVN, reg, 0, imm8, 0, cond)
#define ARM_MVN_REG_IMM8(p, reg, imm8) \
	ARM_MVN_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL)
/* S */
#define ARM_MVNS_REG_IMM8_COND(p, reg, imm8, cond) \
	ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_MVN, reg, 0, imm8, 0, cond)
#define ARM_MVNS_REG_IMM8(p, reg, imm8) \
	ARM_MVNS_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL)

#ifndef ARM_NOIASM
#define _MVN_REG_IMM8_COND(reg, imm8, cond) \
	ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_MVN, reg, 0, imm8, 0, cond)
#define _MVN_REG_IMM8(reg, imm8) \
	_MVN_REG_IMM8_COND(reg, imm8, ARMCOND_AL)
/* S */
#define _MVNS_REG_IMM8_COND(reg, imm8, cond) \
	ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_MVN, reg, 0, imm8, 0, cond)
#define _MVNS_REG_IMM8(reg, imm8) \
	_MVNS_REG_IMM8_COND(reg, imm8, ARMCOND_AL)
#endif


/* Rd := Rm */
#define ARM_MVN_REG_REG_COND(p, rd, rm, cond) \
	ARM_DPIOP_REG_REG_COND(p, ARMOP_MVN, rd, 0, rm, cond)
#define ARM_MVN_REG_REG(p, rd, rm) \
	ARM_MVN_REG_REG_COND(p, rd, rm, ARMCOND_AL)
/* S */
#define ARM_MVNS_REG_REG_COND(p, rd, rm, cond) \
	ARM_DPIOP_S_REG_REG_COND(p, ARMOP_MVN, rd, 0, rm, cond)
#define ARM_MVNS_REG_REG(p, rd, rm) \
	ARM_MVNS_REG_REG_COND(p, rd, rm, ARMCOND_AL)

#ifndef ARM_NOIASM
#define _MVN_REG_REG_COND(rd, rm, cond) \
	ARM_IASM_DPIOP_REG_REG_COND(ARMOP_MVN, rd, 0, rm, cond)
#define _MVN_REG_REG(rd, rm) \
	_MVN_REG_REG_COND(rd, rm, ARMCOND_AL)
/* S */
#define _MVNS_REG_REG_COND(rd, rm, cond) \
	ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_MVN, rd, 0, rm, cond)
#define _MVNS_REG_REG(rd, rm) \
	_MVNS_REG_REG_COND(rd, rm, ARMCOND_AL)
#endif


/* Rd := Rm <shift_type> imm_shift */
#define ARM_MVN_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \
	ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_MVN, rd, 0, rm, shift_type, imm_shift, cond)
#define ARM_MVN_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \
	ARM_MVN_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL)
/* S */
#define ARM_MVNS_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \
	ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_MVN, rd, 0, rm, shift_type, imm_shift, cond)
#define ARM_MVNS_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \
	ARM_MVNS_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL)

#ifndef ARM_NOIASM
#define _MVN_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \
	ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_MVN, rd, 0, rm, shift_type, imm_shift, cond)
#define _MVN_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \
	_MVN_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL)
/* S */
#define _MVNS_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \
	ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_MVN, rd, 0, rm, shift_type, imm_shift, cond)
#define _MVNS_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \
	_MVNS_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL)
#endif



/* Rd := (Rm <shift_type> Rs) */
#define ARM_MVN_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \
	ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_MVN, rd, 0, rm, shift_type, rs, cond)
#define ARM_MVN_REG_REGSHIFT(p, rd, rm, shift_type, rs) \
	ARM_MVN_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL)
/* S */
#define ARM_MVNS_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \
	ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_MVN, rd, 0, rm, shift_type, rs, cond)
#define ARM_MVNS_REG_REGSHIFT(p, rd, rm, shift_type, rs) \
	ARM_MVNS_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL)

#ifndef ARM_NOIASM
#define _MVN_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \
	ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_MVN, rd, 0, rm, shift_type, rs, cond)
#define _MVN_REG_REGSHIFT(rd, rm, shift_type, rs) \
	_MVN_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL)
/* S */
#define _MVNS_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \
	ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_MVN, rd, 0, rm, shift_type, rs, cond)
#define _MVNS_REG_REGSHIFT(rd, rm, shift_type, rs) \
	_MVNS_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL)
#endif



/* DPIs, arithmetic and logical */

/* -- AND -- */

/* Rd := Rn AND (imm8 ROR rot) ; rot is power of 2 */
#define ARM_AND_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
	ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_AND, rd, rn, imm8, rot, cond)
#define ARM_AND_REG_IMM(p, rd, rn, imm8, rot) \
	ARM_AND_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
#define ARM_ANDS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
	ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_AND, rd, rn, imm8, rot, cond)
#define ARM_ANDS_REG_IMM(p, rd, rn, imm8, rot) \
	ARM_ANDS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)

#ifndef ARM_NOIASM
#define _AND_REG_IMM_COND(rd, rn, imm8, rot, cond) \
	ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_AND, rd, rn, imm8, rot, cond)
#define _AND_REG_IMM(rd, rn, imm8, rot) \
	_AND_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
#define _ANDS_REG_IMM_COND(rd, rn, imm8, rot, cond) \
	ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_AND, rd, rn, imm8, rot, cond)
#define _ANDS_REG_IMM(rd, rn, imm8, rot) \
	_ANDS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
#endif


/* Rd := Rn AND imm8 */
#define ARM_AND_REG_IMM8_COND(p, rd, rn, imm8, cond) \
	ARM_AND_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
#define ARM_AND_REG_IMM8(p, rd, rn, imm8) \
	ARM_AND_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
#define ARM_ANDS_REG_IMM8_COND(p, rd, rn, imm8, cond) \
	ARM_ANDS_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
#define ARM_ANDS_REG_IMM8(p, rd, rn, imm8) \
	ARM_ANDS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)

#ifndef ARM_NOIASM
#define _AND_REG_IMM8_COND(rd, rn, imm8, cond) \
	_AND_REG_IMM_COND(rd, rn, imm8, 0, cond)
#define _AND_REG_IMM8(rd, rn, imm8) \
	_AND_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
#define _ANDS_REG_IMM8_COND(rd, rn, imm8, cond) \
	_ANDS_REG_IMM_COND(rd, rn, imm8, 0, cond)
#define _ANDS_REG_IMM8(rd, rn, imm8) \
	_ANDS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
#endif