uart.vhd

用VHDL为MCU编写的可用UART-通用异步收发器程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 entity uart is
   port(  clk:in std_logic;--5部波特率
         reset:in std_logic;
         start:in std_logic;
          din: in std_logic;--输入数据
          dout:out std_logic_vector(7 downto 0):="00000000" );
    end uart;
 architecture rtl of uart is
 type state is(startb,shiftb,stopb);
 signal nextb:state:=startb;
 signal sout:std_logic_vector(7 downto 0);
 begin
    process(reset,clk)
     variable cou,coutp,ct:integer range 0 to 4;
      variable ther:std_logic_vector(3 downto 0);
      begin
        if reset='1' then
          sout<="00000000";
          nextb<=startb;
          ct:=0;cou:=0;coutp:=0;
         elsif clk'event and clk='1' then
            case nextb is
               when startb=>if start='1' then  --检测起始位
                             ther:="0000";
                              if ct=4 then
                                   ct:=0;
                                 if coutp>cou then
                                    nextb<=shiftb;
                                    cou:=0;coutp:=0;
                                 else
                                    cou:=0;coutp:=0;
                                    nextb<=startb;
                                 end if;
                               else
                                 if din='1' then
                                   cou:=cou+1;
                                 else
                                   coutp:=coutp+1;
                                 end if;
                                  ct:=cou+coutp;
                               end if; 
                             end if;
                when shiftb=>if ct=4 then
                                ct:=0;
                                ther:=ther+1;
                                sout(6 downto 0)<=sout(7 downto 1);
                                if coutp>cou then
                                 sout(7)<='0';
                                 cou:=0;coutp:=0;
                                 else
                                  sout(7)<='1';
                                  cou:=0;coutp:=0;
                                 end if;
                              else
                                if din='1' then
                                   cou:=cou+1;
                                 else
                                   coutp:=coutp+1;
                                 end if;
                                  ct:=cou+coutp; 
                              end if;                               
                              if ther=8 then
                                 nextb<=stopb;
                              else
                                 nextb<=shiftb;
                              end if;
                 when stopb=> dout<=sout;
                              nextb<=startb;
            end case;
        end if;
      end process;
   end rtl;