code.v

来自「键盘控制电路」· Verilog 代码 · 共 20 行

//--------------------------------
//Generate scan code
//Filename : CODE.v
//--------------------------------
module CODE(CLK, SCAN_CODE);
input CLK;

output [1:0] SCAN_CODE;
parameter leng=9;
reg [leng-1:0] REG;

always @ (posedge CLK)
  begin
      REG = REG + 9'b01;
  end

assign SCAN_CODE = REG[leng-1:leng-2];

endmodule