debounce.v

来自「键盘控制电路」· Verilog 代码 · 共 44 行

//-------------------------------------------
//Debounce circuit for one key_pressing
//Filename : debounce.v
//-------------------------------------------
module debounce(clk, rst, keyin, K_out);
input clk, rst;
input keyin;
output K_out;


reg DEL1, DEL2, DEL3; // 3-stage delay
wire DJ, DK;

always @(posedge clk or posedge rst)
 begin
   if (rst)
    begin
      DEL1 <= 1'b0;
	 DEL2 <= 1'b0;
	 DEL3 <= 1'b0;
    end
   else
    begin
      if (keyin == 1'b1)
        DEL1 <= 1'b1;
      else
	   DEL1 <=1'b0;
      if (DEL1 ==1'b1)
	   DEL2 <=1'b1;
      else
	   DEL2 <= 1'b0;
      if (DEL2 ==1'b1)
	   DEL3 <=1'b1;
      else
	   DEL3 <= 1'b0;

    end
 end
assign DJ = DEL1 & DEL2 & DEL3;
assign DK = ~(DEL1 | DEL2 | DEL3);
JKFF jkf (.clk(clk), .rst(rst), .j(DJ), .k(DK), .q(K_out));

endmodule