cnt5.v

来自「键盘控制电路」· Verilog 代码 · 共 19 行

//-------------------------
//Clock divided by 32
//Filenale : cnt5.v
//-------------------------
module  cnt5(in,out);
input  in;
output  out;

reg [4:0]out1;

always@(posedge in  )
begin
     out1<= out1 + 5'b1;  
end

assign out = out1[4];

endmodule