time.vhd

来自「EDA技术应用.用QUARTUES II 实现EDA技术实验操作,类似于精典的M」· VHDL 代码 · 共 34 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TIMES IS
  PORT(CLR: IN STD_LOGIC;
       CLK: IN STD_LOGIC;
       ENA: IN STD_LOGIC;
       DOUT: OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END ENTITY TIMES;
ARCHITECTURE ART OF TIMES IS
  COMPONENT CLKGEN IS
      PORT(CLK: IN STD_LOGIC;
           NEWCLK: OUT STD_LOGIC);
      END COMPONENT CLKGEN;
      COMPONENT CNT10 IS
          PORT(CLK, CLR, ENA: IN STD_LOGIC;
               CQ: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
               CARRY_OUT: OUT STD_LOGIC);
      END COMPONENT CNT10;
      COMPONENT CNT6 IS
        PORT(CLK, CLR, ENA: IN STD_LOGIC;
             CQ: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
             CARRY_OUT: OUT STD_LOGIC);
      END COMPONENT CNT6;
      SIGNAL S0: STD_LOGIC;
      SIGNAL S1,S2,S3,S4,S5: STD_LOGIC;
      BEGIN
      U0: CLKGEN PORT MAP(CLK=>CLK,NEWCLK=>S0);
      U1: CNT10 PORT MAP(S0, CLR, ENA, DOUT(3 DOWNTO 0), S1);
      U2: CNT10 PORT MAP(S1, CLR, ENA, DOUT(7 DOWNTO 4), S2);
      U3: CNT10 PORT MAP(S2, CLR, ENA, DOUT(11 DOWNTO 8), S3);
      U4: CNT6 PORT MAP(S3, CLR, ENA, DOUT(15 DOWNTO 12), S4);
      U5: CNT10 PORT MAP(S4, CLR, ENA, DOUT(19 DOWNTO 16), S5);
      U6: CNT6 PORT MAP(S5, CLR, ENA, DOUT(23 DOWNTO 20));
END ARCHITECTURE ART;