正负脉宽数控调制信号发生器的设计.txt

EDA技术应用.用QUARTUES II 实现EDA技术实验操作,类似于精典的MAX+PLUS

1)8位可自加载加法计数器的源程序LCNT8.VHD
LIBRARY IEEE;
USE IEEE.STD-LOGIC-1164, .ALL;
ENTITY  LCNT8  IS
   PORT(CLK, LD: IN STD-LOGIC;
                   D: IN INTEGER RANGE 0TO 255;
                   CAO: OUT STD-LOGIC);
END ENTITY LCNT8;
ARCHITECTURE ART OF LCNT8 IS
SIGNAL COUNT: INTEGER RANGE 0 TO 255;
BEGIN
PROCESS(CLK)IS
BEGIN
        IF CLK'EVENT AND CLK='1' THEN
                 IF LD='1' THEN COUNT<=D;
                        ELSE COUNT<=COUNT+1;
                   END IF;
           END IF;
END PROCESS;
       PROCESS(CLK,COUNT) IS
       BEGIN
              IF CLK'EVENT AND CLK='1' THEN
                 IF COUNT=255 THEN CAO<='1';
                       ELSE CAO<='0';
                  END IF;
             END IF;
END PROCESS;
END ARCHITECTURE ART;

2)正负脉宽数控调制信号发生器的源程序PULSE.VHD
LIBRARY IEEE;
USE IEEE.STD-LOGIC-1164.ALL;
ENTITY PULSE IS
      PORT(CLK: IN STD-LOGIC;
                  A,B: IN STD-LOGIC-VECTOR(7 DOWNTO 0);
                  PSOUT: OUT STD-LOGIC);
END ENTITY PULSE;
ARCHITECTURE ART OF PULSE IS
  COMPONENT LCNT8 IS
              PORT(CLK, LD: IN STD-LOGIC;
                         D: IN STD-LIGIC-VECTOR(7 DOWNTO 0);
                         CAO: OUT STD-LOGIC);
END COMPONENT LCNT8;
SIGNAL CAO1, CAO2 : STD-LOGIC;
SIGNAL LD1, LD2 :STD-LOGIC;
SIGNAL PSINT: STD-LOGIC;
BEGIN
U1: LCNT8 PORT MAP(CLK=>CLK,LD=>LD1,D=>A,CAO=>CAO1);
U2: LCNT8 PORT MAP(CLK=>CLK,LD=>LD2,D=>B,CAO=>CAO2);
BEGIN
IF CAO='1' THEN PSINT<='0';
ELSIF CAO2'EVENT AND CAO2='1' THEN PSINT<='1';
END IF;
END PROCESS;
LD1<=NOT PSINT; LD2<=PSINT; PSOUT<=PSINT;
END ARCHITECTURE ART;