clkgen.vhd

来自「EDA技术应用.用QUARTUES II 实现EDA技术实验操作,类似于精典的M」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CLKGEN IS 
   PORT(CLK: IN STD_LOGIC;
         NEWCLK: OUT STD_LOGIC);
END ENTITY CLKGEN;
ARCHITECTURE ART OF CLKGEN IS
    SIGNAL CNTER:INTEGER RANGE 0 TO 10#29999#;
         BEGIN
         PROCESS(CLK) IS
         BEGIN IS
            IF CLK'EVENT AND CLK='1' THEN
                 IF CNTER=10#29999#THEN CNTER<=0;
                 ELSE CNTER<=CNTER+1;
                 END IF;
            END IF;
         END PROCESS;
    PROCESS(CNTER) IS
    BEGIN
         IF CNTER=10#29999#THEN NEWCLK<='1';
         ELSE NEWCLK<='0'
         END IF;
    END PROCESS;
END ARCHITECTURE ART;