ndotxfd.vhd

可实现任意一位小数分频,在quartus II中仿真验证通过,输入端N为分频系数的十位数,X为分频系数的个位数.

----------------------------------------------------------------------------------
-- Company: 		Hiline
-- Engineer: 		Liu Xiting
-- Email:			[e-mail];[e-mail]
-- 
-- Create Date:     21:13:54 01/03/2008 
-- Design Name: 	N.x frequency deviation
-- Module Name:		NdotXfd 
-- Project Name:	NdotXfd
-- Target Devices:	EP1C6Q240C8 or other FPGA/CPLD Device
-- Tool versions: 	Quartus II 7.2
-- Description:		Topview of the project
--
-- Dependencies: 
--
-- Revision:		V1.0
--
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity NdotXfd is
	port (
		clock		: in  std_logic;
		n			: in  std_logic_vector(3 downto 0);
		x           : in  std_logic_vector(3 downto 0);
		clock_out   : out std_logic
	);
end entity;

architecture arch of NdotXfd is

	component number
	port(
		n		: in  std_logic_vector(3 downto 0);
		number0 : out std_logic_vector(3 downto 0);
		number1 : out std_logic_vector(3 downto 0)
	);
	end component;
	
	component fdn
    port(
		clock_in	: in  std_logic;
		enable		: in  std_logic;
		n_of_fd		: in  std_logic_vector(3 downto 0);
		clock_out	: out std_logic
	);
	end component;
	
	component sel
	port(
		clock_in	: in std_logic;
		Xnumber		: in std_logic_vector(3 downto 0);
		sel_out		: out std_logic
	);
	end component;

	component mux_21
	port(
		a	: in  std_logic;
		b	: in  std_logic;
		s	: in  std_logic;
		y	: out std_logic
	);
	end component;

	signal selt		: std_logic;
	signal selt_not : std_logic;
	signal clock_1	: std_logic;
	signal clock_2	: std_logic;
	signal clock_sel: std_logic;
	signal n_fd		: std_logic_vector(3 downto 0);
	signal n1_fd	: std_logic_vector(3 downto 0);

	begin
	
	number0 : number port map (n, n_fd, n1_fd);
	fdn0	: fdn    port map (clock, selt_not, n_fd, clock_1);
	fdn1	: fdn    port map (clock, selt, n1_fd, clock_2);
    mux_210 : mux_21 port map (clock_2, clock_1, selt, clock_sel);
    sel0	: sel    port map (clock_sel, x, selt);

	selt_not <= not selt;
	clock_out <= clock_sel;

end arch;