fdn.vhd

可实现任意一位小数分频,在quartus II中仿真验证通过,输入端N为分频系数的十位数,X为分频系数的个位数.

----------------------------------------------------------------------------------
-- Company: 		Hiline
-- Engineer: 		Liu Xiting
-- Email:			[e-mail];[e-mail]
-- 
-- Create Date:     21:13:54 01/03/2008 
-- Design Name: 	N.x frequency deviation
-- Module Name:		fdn 
-- Project Name:	NdotXfd
-- Target Devices:	EP1C6Q240C8 or other FPGA/CPLD Device
-- Tool versions: 	Quartus II 7.2
-- Description:		natural coefficient frequency deviation
--
-- Dependencies:	The input n_of_fd must be natural number 
--
-- Revision:		V1.0
--
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fdn is
  port
  (
    clock_in  : in  std_logic;
    enable    : in  std_logic;
    n_of_fd	  : in  std_logic_vector(3 downto 0);
    clock_out : out std_logic
  );
end entity;

architecture bhv of fdn is

  
  signal clock    : std_logic;
  signal q0       : std_logic;
  signal q1       : std_logic;
  signal number   : std_logic_vector(2 downto 0);
  signal counter0 : std_logic_vector(3 downto 0);
  signal counter1 : std_logic_vector(3 downto 0);

begin

  fdn: process(enable, clock_in, n_of_fd, clock, q0, q1)
  begin

    number(2 downto 0) <= n_of_fd(3 downto 1);

	if q1 = '0' then
      clock <= not clock_in;
    else
      clock <= clock_in;
    end if;
  
  if (enable='1') then
    if (n_of_fd(0)='0')then
      counter1 <= (others=>'0');
      q1 <= '0';
      if rising_edge(clock_in) then
        if (number="001") then
          q0 <= not q0;
        else
	      if counter0 = number-1 then
            counter0 <= (others=>'0');
            q0 <= not q0;
          else
            counter0 <= counter0 + 1;
          end if;
        end if;
      end if;
    else
      counter0 <= (others=>'0');
      q0 <= '0'; 
      if rising_edge(clock) then
	    if counter1 = number then
          counter1 <= (others=>'0');
          q1 <= not q1;
        else
          counter1 <= counter1 + 1;
        end if;
      end if;
    end if;
  else
    q0 <= '0';
    q1 <= '0';
    counter0 <= (others=>'0');
    counter1 <= (others=>'0');
  end if;
  end process fdn;

  output: process (enable, n_of_fd(0), q0, q1)
  begin
    if (enable='1') then
      if (n_of_fd(0)='0')then
        clock_out <= q0;
      else
        clock_out <= q1;
     end if;
    else
      clock_out <= '0';
    end if;
  end process output;
  
end bhv;