📄 number.vhd
字号:
----------------------------------------------------------------------------------
-- Company: Hiline
-- Engineer: Liu Xiting
-- Email: Liu_xitin@163.com;liuxiting@foxmail.com
--
-- Create Date: 21:13:54 01/03/2008
-- Design Name: N.x frequency deviation
-- Module Name: number
-- Project Name: NdotXfd
-- Target Devices: EP1C6Q240C8 or other FPGA/CPLD Device
-- Tool versions: Quartus II 7.2
-- Description: coefficient of fdn;
-- number0 is the coefficient of fdn;
-- numger1 is the coefficient of fdn1(number1=number0+1);
--
-- Dependencies:
--
-- Revision: V1.0
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity number is
port
( n : in std_logic_vector(3 downto 0);
number0 : out std_logic_vector(3 downto 0);
number1 : out std_logic_vector(3 downto 0)
);
end entity;
architecture bhv of number is
begin
number0 <= n;
number1 <= n+1;
end bhv;
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