top.ucf

开发环境ise6+

############################################################################
##
##  Xilinx, Inc. 2002            www.xilinx.com
##
##  XAPP 266 - Synthesizable FCRAM Controller
##
############################################################################
##  File name :       top.ucf
## 
##  Description :     Constraints file
##                    XAPP 266, targetted to XC2V3000-5-FF1152
##                    Synthesized with Synplify, v6.2
## 
##  Date - revision : 01/15/2002 - v 1.0
##
##  Author :          CLF
##
############################################################################

############################################################################
# Device selection
############################################################################
CONFIG PART = XC2V3000-5-FF1152;

############################################################################
# Clock constraints                                                        #
############################################################################
# CLOCK PERIOD = 154 MHz
NET "sys_clk" TNM_NET = "sys_clk";
TIMESPEC "TS_SYS_CLK" = PERIOD "sys_clk" 6.40 ns HIGH 50 %;

# CREATE TNMs
NET "ddr_dqs[*]"                            TNM_NET = DQS;
PIN "U_fcram_cntrl/U_clk_dcm/DCM_CLK.CLK0"  TNM     = CLK0; 
PIN "U_fcram_cntrl/U_clk_dcm/DCM_RCLK.CLK0" TNM     = RCLK;

# CROSS CLOCK DOMAIN, FROM CLK TO RCLK, FROM RCLK TO CLK
#  All transfers from CLK to RCLK and from RCLK to CLK are guaranteed to 
#  be stable (transfer is always double-registered). Therefore, the 
#  timing tools should not analyze these paths.
TIMESPEC TS_IGNORE1 = FROM CLK0 TO RCLK TIG; 
TIMESPEC TS_IGNORE2 = FROM RCLK TO CLK0 TIG;

# CROSS CLOCK DOMAIN, FROM DQS TO RCLK
#  As described in the application note, the path from DQS to the recapture
#  clock must be constrained. If these signals were exactly in phase, this
#  would be set to one clock period. A worst-case analysis assuming a 
#  prorating factor of 25% gives the following relationship.
TIMESPEC TS_DQS_2_RCLK = FROM DQS TO RCLK 2.5 ns; 

# CROSS CLOCK DOMAIN, FROM CLK90 TO DQS
#  The read enable logic is generated by the controller off of CLK90. 
#  Therefore, the path from CLK90 to DQS must be constrained. By design,
#  the read enable will always turn on early and off late, and therefore
#  the constraint is set to one clock period.
PIN "U_fcram_cntrl/U_clk_dcm/DCM_CLK.CLK90" TNM = CLK90;
TIMESPEC TS_CLK90_2_DQS = FROM CLK90 TO DQS 6.4 ns;

# RECAPTURE CLOCK PHASE SHIFT
#  This should be set by the user as described in the application note
INST "U_fcram_cntrl/U_clk_dcm/DCM_RCLK" CLKOUT_PHASE_SHIFT = FIXED;
INST "U_fcram_cntrl/U_clk_dcm/DCM_RCLK" PHASE_SHIFT        = 140;

############################################################################
# GENERATE TIMEGROUPS                                                      #
############################################################################
# FCRAM Interface
INST "ddr_ad[*].PAD"         TNM = "ADDR_PAD" ;
INST "ddr_ba[*].PAD"         TNM = "ADDR_PAD" ;
INST "ddr_dq[*].PAD"         TNM = "DQ_PAD"   ;
INST "ddr_dqs*.PAD"          TNM = "DQS_PAD"  ;
INST "ddr_fn.PAD"            TNM = "CNTRL_PAD";
INST "ddr_pdb.PAD"           TNM = "CNTRL_PAD";
INST "ddr_csb.PAD"           TNM = "CNTRL_PAD";
INST "ddr_clk.PAD"           TNM = "CLK_PAD"  ;
INST "ddr_clkb.PAD"          TNM = "CLKB_PAD" ;
# User Interface
INST "sys_ack.PAD"           TNM = "USER_PAD" ;
INST "sys_addr[*].PAD"       TNM = "USER_PAD" ;
INST "sys_cmd[*].PAD"        TNM = "USER_PAD" ;
INST "sys_data_i[*].PAD"     TNM = "USER_PAD" ;
INST "sys_data_o[*].PAD"     TNM = "USER_PAD" ;
INST "sys_data_req.PAD"      TNM = "USER_PAD" ;
INST "sys_data_val.PAD"      TNM = "USER_PAD" ;
INST "sys_init_parms[*].PAD" TNM = "USER_PAD" ;
INST "sys_num_xfers[*].PAD"  TNM = "USER_PAD" ;
INST "sys_ref_enable.PAD"    TNM = "USER_PAD" ;
INST "sys_ref_parms[*].PAD"  TNM = "USER_PAD" ;

############################################################################
# ROUTING CONSTRAINTS                                                      #
############################################################################
# DQS CONSTRAINTS
#  This constrains the distribution of DQS on the local clocking structures
NET "U_fcram_cntrl/dqs[?]" MAXSKEW  = 100ps; 
NET "U_fcram_cntrl/dqs[?]" MAXDELAY = 370ps; 

# RESET CONSTRAINTS 
NET "sys_reset_n"          MAXDELAY = 4ns;

############################################################################
# I/O TIMING CONSTRAINTS                                                   #
############################################################################
TIMEGRP "USER_PAD" OFFSET = IN 5.0 ns BEFORE "sys_clk";
OFFSET = IN 1 ns BEFORE "ddr_dqs[0]";
OFFSET = IN 1 ns BEFORE "ddr_dqs[1]";

TIMEGRP "ADDR_PAD"  OFFSET = OUT 9.8 ns AFTER "sys_clk";
TIMEGRP "CNTRL_PAD" OFFSET = OUT 9.8 ns AFTER "sys_clk";
TIMEGRP "USER_PAD"  OFFSET = OUT 5.0 ns AFTER "sys_clk";
TIMEGRP "DQ_PAD"    OFFSET = OUT 9.8 ns AFTER "sys_clk";

############################################################################
# I/O STANDARDS                                                            #
############################################################################
# SSTL2_I for input or output signals
NET "ddr_ad[*]"  IOSTANDARD = SSTL2_I;
NET "ddr_ba[*]"  IOSTANDARD = SSTL2_I;
NET "ddr_fn"     IOSTANDARD = SSTL2_I;
NET "ddr_pdb"    IOSTANDARD = SSTL2_I;
NET "ddr_csb"    IOSTANDARD = SSTL2_I;
NET "ddr_clk"    IOSTANDARD = SSTL2_I;
NET "ddr_clkb"   IOSTANDARD = SSTL2_I;
# SSTL_II for bi-directional signals
NET "ddr_dq[*]"  IOSTANDARD = SSTL2_II;
NET "ddr_dqs*"   IOSTANDARD = SSTL2_II;

# Place holder for user interface
NET "sys_*"      IOSTANDARD = SSTL2_II;

############################################################################
# I/O LOCATION CONSTRAINTS                                                 #
############################################################################

# BYTE 1
NET "ddr_dqs[1]" LOC = "AB30";
NET "ddr_dq[15]" LOC = "V34";
NET "ddr_dq[14]" LOC = "V33";
NET "ddr_dq[13]" LOC = "V28";
NET "ddr_dq[12]" LOC = "W28";
NET "ddr_dq[11]" LOC = "AA33";
NET "ddr_dq[10]" LOC = "AB33";
NET "ddr_dq[9]"  LOC = "Y29";
NET "ddr_dq[8]"  LOC = "Y28";

# BYTE 0
NET "ddr_dqs[0]" LOC = "AD31";
NET "ddr_dq[7]"  LOC = "AA29";
NET "ddr_dq[6]"  LOC = "AB29";
NET "ddr_dq[5]"  LOC = "W27";
NET "ddr_dq[4]"  LOC = "Y27";
NET "ddr_dq[3]"  LOC = "AC34";
NET "ddr_dq[2]"  LOC = "AD34";
NET "ddr_dq[1]"  LOC = "Y26";
NET "ddr_dq[0]"  LOC = "AA26";

# Add no delay attribute to data paths
NET "ddr_dq[*]"  IOBDELAY = NONE;

############################################################################
# USER INTERFACE                                                           #
############################################################################
# Add IOB = FALSE for user input signals
INST "U_fcram_cntrl/U_data_path/u_data_i_P1[*]"       IOB = FALSE;
INST "U_fcram_cntrl/U_addr_cntrl/burst_length_int[*]" IOB = FALSE;
INST "U_fcram_cntrl/U_addr_cntrl/cas_latency_int[*]"  IOB = FALSE;
INST "U_user_int/sys_addr_P1[*]"                      IOB = FALSE;
NET  "sys_*"                                          IOBDELAY = NONE;

############################################################################
# PLACEMENT CONSTRAINTS                                                    #
############################################################################
# FIFO Area Group Placement Constraints
#  PAR can have a difficult time placing dual-port LUT RAM. This eases the 
#  aids PAR, and helps with the timing of the TS_DQS_2_RCLK constraint. 
#  It simply creates an area group near the IOs.
INST "U_fcram_cntrl/U_data_path/SYNCH0/mem*" AREA_GROUP =  AG_FCRAM_FIFO ;
AREA_GROUP "AG_FCRAM_FIFO" RANGE = SLICE_X0Y42:SLICE_X3Y59 ;

############################################################################
# SAMPLE CONSTRAINTS                                                       #
#   This gives additional sample pin locations for valid DQS and DQ        #
#   placement for the FF1152 package.                                      # 
############################################################################

# BYTE 8
# NET "ddr_dqs[8]" LOC = "F31"
# NET "ddr_dq[71]" LOC = "E34"
# NET "ddr_dq[70]" LOC = "D34"
# NET "ddr_dq[69]" LOC = "K24"
# NET "ddr_dq[68]" LOC = "L25"
# NET "ddr_dq[67]" LOC = "E32"
# NET "ddr_dq[66]" LOC = "D32"
# NET "ddr_dq[65]" LOC = "J26"
# NET "ddr_dq[64]" LOC = "K27"

# BYTE 7
# NET "ddr_dqs[7]" LOC = "J29"
# NET "ddr_dq[63]" LOC = "G33"
# NET "ddr_dq[62]" LOC = "F33"
# NET "ddr_dq[61]" LOC = "K26"
# NET "ddr_dq[60]" LOC = "L26"
# NET "ddr_dq[59]" LOC = "H29"
# NET "ddr_dq[58]" LOC = "G29"
# NET "ddr_dq[57]" LOC = "L28"
# NET "ddr_dq[56]" LOC = "K28"

# BYTE 6
# NET "ddr_dqs[6]" LOC = "J31"
# NET "ddr_dq[55]" LOC = "G34"
# NET "ddr_dq[54]" LOC = "F34"
# NET "ddr_dq[53]" LOC = "M25"
# NET "ddr_dq[52]" LOC = "N25"
# NET "ddr_dq[51]" LOC = "G32"
# NET "ddr_dq[50]" LOC = "F32"
# NET "ddr_dq[49]" LOC = "L27"
# NET "ddr_dq[48]" LOC = "M27"

# BYTE 5
# NET "ddr_dqs[5]" LOC = "K31"
# NET "ddr_dq[47]" LOC = "K33"
# NET "ddr_dq[46]" LOC = "J33"
# NET "ddr_dq[45]" LOC = "M26"
# NET "ddr_dq[44]" LOC = "N26"
# NET "ddr_dq[43]" LOC = "J32"
# NET "ddr_dq[42]" LOC = "H32"
# NET "ddr_dq[41]" LOC = "N28"
# NET "ddr_dq[40]" LOC = "M28"

# BYTE 4
# NET "ddr_dqs[4]" LOC = "M32"
# NET "ddr_dq[39]" LOC = "M33"
# NET "ddr_dq[38]" LOC = "L33"
# NET "ddr_dq[37]" LOC = "L30"
# NET "ddr_dq[36]" LOC = "K29"
# NET "ddr_dq[35]" LOC = "M31"
# NET "ddr_dq[34]" LOC = "L31"
# NET "ddr_dq[33]" LOC = "N27"
# NET "ddr_dq[32]" LOC = "P27"

# BYTE 3
# NET "ddr_dqs[3]" LOC = "P31"
# NET "ddr_dq[31]" LOC = "M34"
# NET "ddr_dq[30]" LOC = "L34"
# NET "ddr_dq[29]" LOC = "P25"
# NET "ddr_dq[28]" LOC = "R25"
# NET "ddr_dq[27]" LOC = "P30"
# NET "ddr_dq[26]" LOC = "N30"
# NET "ddr_dq[25]" LOC = "P26"
# NET "ddr_dq[24]" LOC = "R26"

# BYTE 2
# NET "ddr_dqs[2]" LOC = "U30"
# NET "ddr_dq[23]" LOC = "P33"
# NET "ddr_dq[22]" LOC = "N33"
# NET "ddr_dq[21]" LOC = "R27"
# NET "ddr_dq[20]" LOC = "T27"
# NET "ddr_dq[19]" LOC = "P32"
# NET "ddr_dq[18]" LOC = "N32"
# NET "ddr_dq[17]" LOC = "U26"
# NET "ddr_dq[16]" LOC = "U27"