clk_dcm.v

开发环境ise6+

/******************************************************************************
**
**  Xilinx, Inc. 2002                 www.xilinx.com
**
**  XAPP 266 - Synthesizable FCRAM Controller
**
*******************************************************************************
**
**  File name :       clk_dcm.v
**
**  Description :     clk_dcm contain 2 DCMs
**                    The first DCM, DCM_CLK, is used as the internal
**                    system clock. This DCM generates clk and clk90 used
**                    for the main controller and data paths. This DCM also
**                    generates clocks sent to the FCRAM through DDR IOB FFs.
**                    The second DCM, DCM_RCLK, generates the recapture clock.
**                    During a read, because data is captured by the DQS
**                    signal, it must be immediately recaptured. This DCM
**                    uses a phase shift attribute to allow a designer to 
**                    tune the positioning of the recapture clock (rclk) to 
**                    their specific board design. The transfer of data from 
**                    recapture to the system clock domain is handled by the 
**                    data_path module.
**                    Finally, a copy of the internal system clock (fpga_clk)
**                    is returned to the user application.
**
**  Date - revision : 01/15/2002 - v 1.0
**
**  Author :          CLF
**
**  Contact : e-mail  [e-mail]
**            phone   + 1 800 255 7778 
**
**  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 
**              provided to you "as is". Xilinx and its licensors make and you 
**              receive no warranties or conditions, express, implied, 
**              statutory or otherwise, and Xilinx specifically disclaims any 
**              implied warranties of merchantability, non-infringement, or 
**              fitness for a particular purpose. Xilinx does not warrant that 
**              the functions contained in these designs will meet your 
**              requirements, or that the operation of these designs will be 
**              uninterrupted or error free, or that defects in the Designs 
**              will be corrected. Furthermore, Xilinx does not warrant or 
**              make any representations regarding use or the results of the 
**              use of the designs in terms of correctness, accuracy, 
**              reliability, or otherwise. 
**
**              LIMITATION OF LIABILITY. In no event will Xilinx or its 
**              licensors be liable for any loss of data, lost profits, cost 
**              or procurement of substitute goods or services, or for any 
**              special, incidental, consequential, or indirect damages 
**              arising from the use or operation of the designs or 
**              accompanying documentation, however caused and on any theory 
**              of liability. This limitation will apply even if Xilinx 
**              has been advised of the possibility of such damage. This 
**              limitation shall apply not-withstanding the failure of the 
**              essential purpose of any limited remedies herein. 
**
**  Copyright