data_strobe.v

开发环境ise6+

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**  Xilinx, Inc. 2002                 www.xilinx.com
**
**  XAPP 266 - Synthesizable FCRAM Controller
**
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**
**  File name :       data_strobe.v
**
**  Description :     DQS generation
**		              This block generates the DQS logic. The DQS output is
**                    generated based off the dqs_reset and dqs_enable control
**                    signals from the controller block. The dqs_reset signals 
**                    holds the DQS DDR flip-flop in reset. This guarantees 
**                    that the DQS preamble will be met according to the FCRAM 
**                    specification. The dqs_enable signal drives the 
**                    tri-state flip flop. 
**                    This module also contains the input buffer through 
**                    which DQS is distributed as a clock to the DQ loads
**
**  Date - revision : 01/15/2002 - v 1.0
**
**  Author :          CLF
**
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