controller.v

来自「开发环境ise6+」· Verilog 代码 · 共 54 行

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**
**  Xilinx, Inc. 2002                 www.xilinx.com
**
**  XAPP 266 - Synthesizable FCRAM Controller
**
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**
**  File name :       controller.v
**
**  Description :     Main FCRAM controller block. This includes the following
**                    features:
**                    - The main controller state machine that controlls the 
**                    initialization process upon power up, as well as the 
**                    read, write, and refresh commands. 
**                    - Accepts and decodes the user commands.
**                    - Generates all FCRAM commands via the three
**                    FCRAM control pins (PDB, CSB, FN).
**                    - Generates control signals for other modules, including
**                    the control signals for the dqs_en block.
**
**  Date - revision : 01/15/2002 - v 1.0
**
**  Author :          CLF
**
**  Contact : e-mail  [e-mail]
**            phone   + 1 800 255 7778 
**
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