define.v

开发环境ise6+

`timescale 100 ps / 10 ps

/***********************************************************************\
 * MEMORY SIZE
\***********************************************************************/
`define DDR_DATA_WIDTH    16
`define SYS_DATA_WIDTH    `DDR_DATA_WIDTH*2

/***********************************************************************\
 * SYSTEM DEFITIONS
\***********************************************************************/

// Width of data transfer (u_num_xfers_ bus
`define XFERS             4

// Address Parameters
`define ROW_ADDR_WIDTH    15
`define COL_ADDR_WIDTH    10
`define BNK_ADDR_WIDTH    2
`define SYS_ADDR_WIDTH    `ROW_ADDR_WIDTH + `COL_ADDR_WIDTH + `BNK_ADDR_WIDTH 

//Controller states
`define CTLR_RESET_IDLE         1   // 00000001h
`define CTLR_RDA_INIT           2   // 00000002h
`define CTLR_MRS_INIT           3   // 00000004h
`define CTLR_IDLE_INIT          4   // 00000008h
`define CTLR_IDLE_INIT_2        5   // 00000010h
`define CTLR_IDLE               6   // 00000020h
`define CTLR_WRA_0              7   // 00000040h
`define CTLR_WRA_0A             8   // 00000080h
`define CTLR_WRITE_0            9   // 00000100h
`define CTLR_WRA_1              10  // 00000200h
`define CTLR_WRITE_1            11  // 00000400h
`define CTLR_RDA_0              12  // 00000800h
`define CTLR_READ_0             13  // 00001000h
`define CTLR_RDA_1              14  // 00002000h
`define CTLR_READ_1             15  // 00004000h
`define CTLR_REF_WRITE_ACTIVE   16  // 00008000h
`define CTLR_REF_AUTO_REFRESH   17  // 00010000h
`define CTLR_REF_IDLE           18  // 00020000h
`define CTLR_CONFLICT1_IDLE     19  // 00040000h
`define CTLR_CONFLICT2_IDLE     20  // 00080000h
`define CTLR_IRC_IDLE1          21  // 00100000h
`define CTLR_IRC_IDLE2          22  // 00200000h
`define CTLR_SELF_REF_WRA       23  // 00400000h
`define CTLR_SELF_REFRESH       24  // 00800000h
`define CTLR_SELF_REF_IDLE      25  // 01000000h
`define CTLR_SELF_EXIT          26  // 02000000h
`define CTLR_AUTO_REF_WRA       27  // 04000000h
`define CTLR_AUTO_REFRESH       28  // 08000000h
`define CTLR_AUTO_IDLE          29  // 10000000h

//Refresh controller state definitions
`define REF_IDLE	3'd0
`define REF_WAIT	3'd1
`define REF_REFRESH	3'd2
`define REF_BURST	3'd3
`define REF_INIT        3'd4

//Define Mode Register Set Cycle Time
//  Uses IRSC=5 as suggested by the FCRAM specification. This should not
//  be changed by the user. If it is, the reset condition will be violated.
`define IRSC     4

//Define simulation delays
// These allow functional simulation to align with timing simulation
// They also guarantee the I/O timing is met 

// Clock to output delay, SSTL-II IO
// Values from Virtex-II Datasheet, v1.6
  `define TIOCKP  22  // 2.99 - 0.08

// Internal and board delay route delays for data strobe
  `define ROUTE_DELAY 4 
  `define BOARD_DELAY 8