fcram.prj

开发环境ise6+

#-- Synplicity, Inc.
#-- Version 6.2

#add_file options
add_file -verilog "$LIB/xilinx/virtex2.v"
add_file -verilog "../src/user_application/user_int_impl.v"
add_file -verilog "../src/clk_dcm.v"
add_file -verilog "../src/controller.v"
add_file -verilog "../src/data_path.v"
add_file -verilog "../src/data_strobe.v"
add_file -verilog "../src/fcram_cntrl.v"
add_file -verilog "../src/refresh_cntrl.v"
add_file -verilog "../src/addr_cntrl.v"
add_file -verilog "../src/top.v"

#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology VIRTEX2
set_option -part XC2V3000
set_option -package FF1152
set_option -speed_grade -5

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 0
set_option -resource_sharing 0

#map options
set_option -frequency 155.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -modular 0
set_option -retiming 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 0

#set result format/file last
project -result_file "rev_1/top.edf"