traffic.v

来自「１．设计目的 （１）设计交通灯控制器； （２）学习状态机的设计方法； （３」· Verilog 代码 · 共 81 行

module traffic(clk,esp,lightR,lightY,lightG);
input clk,esp;
output[3:0] lightR; //红灯
output[3:0] lightG; //绿灯
output[3:0] lightY; //黄灯
reg[3:0] lightR;
reg[3:0] lightG;
reg[3:0] lightY;
reg[3:0] state;

parameter 
IDLE='d0, A='d1, B='d2,C='d3, D='d4,E='d5, F='d6,G='d7;

always @(posedge clk)
if(!esp)
begin
lightR<=4'b1111;//紧急事件，红灯全亮
lightG<=4'b0;
lightY<=4'b0;
end
else
case(state)
IDLE : 
begin
lightR<=4'b1100;
lightG<=4'b0;
lightY<=4'b0011;
state <= A;
end
A:  
begin
lightR<=4'b1100;
lightG<=4'b0011;
lightY<=4'b0;
state <=B;
end
B:  
begin
lightR<=4'b0;
lightG<=4'b1111;
lightY<=4'b0;
state <= C;
end
C:  
begin
lightR<=4'b0011;
lightG<=4'b1100;
lightY<=4'b0;
state <= D;
end
D:  
begin
lightR<=4'b0011;
lightG<=4'b0;
lightY<=4'b0011;
state <= E;
end
E:  
begin
lightR<=4'b0011;
lightG<=4'b0011;
lightY<=4'b0;
state <= F;
end
F: 
begin
lightR<=4'b0;
lightG<=4'b1111;
lightY<=4'b0;
state <= G;
end
G:  
begin
lightR<=4'b1100;
lightG<=4'b0011;
lightY<=4'b0;
state <= A;
end
default:state<=IDLE;//返回初始状态。
endcase
endmodule