traffic.tan.qmsg

１．设计目的 （１）设计交通灯控制器； （２）学习状态机的设计方法； （３）学习原理图、状态机等多种的设计方法进行混合设计； （４）熟练掌握器件设计输入、编译、仿真和编程的过程。 ２．设计内

{ "Info" "ITDB_TSU_RESULT" "state.D esp clk 3.688 ns register " "Info: tsu for register \"state.D\" (data pin = \"esp\", clock pin = \"clk\") is 3.688 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.798 ns + Longest pin register " "Info: + Longest pin to register delay is 5.798 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns esp 1 PIN PIN_88 13 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_88; Fanout = 13; PIN Node = 'esp'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { esp } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.996 ns) + CELL(0.667 ns) 5.798 ns state.D 2 REG LC_X17_Y13_N3 4 " "Info: 2: + IC(3.996 ns) + CELL(0.667 ns) = 5.798 ns; Loc. = LC_X17_Y13_N3; Fanout = 4; REG Node = 'state.D'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "4.663 ns" { esp state.D } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.802 ns ( 31.08 % ) " "Info: Total cell delay = 1.802 ns ( 31.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.996 ns ( 68.92 % ) " "Info: Total interconnect delay = 3.996 ns ( 68.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "5.798 ns" { esp state.D } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "5.798 ns" { esp esp~out0 state.D } { 0.000ns 0.000ns 3.996ns } { 0.000ns 1.135ns 0.667ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.139 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 13 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 13; CLK Node = 'clk'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns state.D 2 REG LC_X17_Y13_N3 4 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y13_N3; Fanout = 4; REG Node = 'state.D'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "1.009 ns" { clk state.D } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk state.D } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 state.D } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "5.798 ns" { esp state.D } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "5.798 ns" { esp esp~out0 state.D } { 0.000ns 0.000ns 3.996ns } { 0.000ns 1.135ns 0.667ns } } } { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk state.D } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 state.D } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lightG\[1\] lightG\[1\]~reg0 5.756 ns register " "Info: tco from clock \"clk\" to destination pin \"lightG\[1\]\" through register \"lightG\[1\]~reg0\" is 5.756 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.139 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 13 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 13; CLK Node = 'clk'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns lightG\[1\]~reg0 2 REG LC_X17_Y13_N9 2 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y13_N9; Fanout = 2; REG Node = 'lightG\[1\]~reg0'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "1.009 ns" { clk lightG[1]~reg0 } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk lightG[1]~reg0 } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 lightG[1]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.444 ns + Longest register pin " "Info: + Longest register to pin delay is 3.444 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lightG\[1\]~reg0 1 REG LC_X17_Y13_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y13_N9; Fanout = 2; REG Node = 'lightG\[1\]~reg0'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { lightG[1]~reg0 } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.822 ns) + CELL(1.622 ns) 3.444 ns lightG\[1\] 2 PIN PIN_91 0 " "Info: 2: + IC(1.822 ns) + CELL(1.622 ns) = 3.444 ns; Loc. = PIN_91; Fanout = 0; PIN Node = 'lightG\[1\]'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "3.444 ns" { lightG[1]~reg0 lightG[1] } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns ( 47.10 % ) " "Info: Total cell delay = 1.622 ns ( 47.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.822 ns ( 52.90 % ) " "Info: Total interconnect delay = 1.822 ns ( 52.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "3.444 ns" { lightG[1]~reg0 lightG[1] } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "3.444 ns" { lightG[1]~reg0 lightG[1] } { 0.000ns 1.822ns } { 0.000ns 1.622ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk lightG[1]~reg0 } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 lightG[1]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } } { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "3.444 ns" { lightG[1]~reg0 lightG[1] } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "3.444 ns" { lightG[1]~reg0 lightG[1] } { 0.000ns 1.822ns } { 0.000ns 1.622ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "lightY\[1\]~reg0 esp clk -3.235 ns register " "Info: th for register \"lightY\[1\]~reg0\" (data pin = \"esp\", clock pin = \"clk\") is -3.235 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.139 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 13 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 13; CLK Node = 'clk'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns lightY\[1\]~reg0 2 REG LC_X17_Y13_N7 2 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y13_N7; Fanout = 2; REG Node = 'lightY\[1\]~reg0'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "1.009 ns" { clk lightY[1]~reg0 } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk lightY[1]~reg0 } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 lightY[1]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.386 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.386 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns esp 1 PIN PIN_88 13 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_88; Fanout = 13; PIN Node = 'esp'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { esp } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.883 ns) + CELL(0.368 ns) 5.386 ns lightY\[1\]~reg0 2 REG LC_X17_Y13_N7 2 " "Info: 2: + IC(3.883 ns) + CELL(0.368 ns) = 5.386 ns; Loc. = LC_X17_Y13_N7; Fanout = 2; REG Node = 'lightY\[1\]~reg0'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "4.251 ns" { esp lightY[1]~reg0 } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.503 ns ( 27.91 % ) " "Info: Total cell delay = 1.503 ns ( 27.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.883 ns ( 72.09 % ) " "Info: Total interconnect delay = 3.883 ns ( 72.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "5.386 ns" { esp lightY[1]~reg0 } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "5.386 ns" { esp esp~out0 lightY[1]~reg0 } { 0.000ns 0.000ns 3.883ns } { 0.000ns 1.135ns 0.368ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk lightY[1]~reg0 } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 lightY[1]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } } { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "5.386 ns" { esp lightY[1]~reg0 } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "5.386 ns" { esp esp~out0 lightY[1]~reg0 } { 0.000ns 0.000ns 3.883ns } { 0.000ns 1.135ns 0.368ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 02 11:39:29 2008 " "Info: Processing ended: Wed Jan 02 11:39:29 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}