traffic.tan.qmsg

１．设计目的 （１）设计交通灯控制器； （２）学习状态机的设计方法； （３）学习原理图、状态机等多种的设计方法进行混合设计； （４）熟练掌握器件设计输入、编译、仿真和编程的过程。 ２．设计内

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1.18 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1.18 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 02 11:39:29 2008 " "Info: Processing started: Wed Jan 02 11:39:29 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off traffic -c traffic --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off traffic -c traffic --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 2 -1 0 } } { "e:/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register state.D lightY\[1\]~reg0 405.19 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 405.19 MHz between source register \"state.D\" and destination register \"lightY\[1\]~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.234 ns 1.234 ns 2.468 ns " "Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.895 ns + Longest register register " "Info: + Longest register to register delay is 0.895 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.D 1 REG LC_X17_Y13_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y13_N3; Fanout = 4; REG Node = 'state.D'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { state.D } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.467 ns) 0.895 ns lightY\[1\]~reg0 2 REG LC_X17_Y13_N7 2 " "Info: 2: + IC(0.428 ns) + CELL(0.467 ns) = 0.895 ns; Loc. = LC_X17_Y13_N7; Fanout = 2; REG Node = 'lightY\[1\]~reg0'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "0.895 ns" { state.D lightY[1]~reg0 } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.467 ns ( 52.18 % ) " "Info: Total cell delay = 0.467 ns ( 52.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.428 ns ( 47.82 % ) " "Info: Total interconnect delay = 0.428 ns ( 47.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "0.895 ns" { state.D lightY[1]~reg0 } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "0.895 ns" { state.D lightY[1]~reg0 } { 0.000ns 0.428ns } { 0.000ns 0.467ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.139 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 13 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 13; CLK Node = 'clk'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns lightY\[1\]~reg0 2 REG LC_X17_Y13_N7 2 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y13_N7; Fanout = 2; REG Node = 'lightY\[1\]~reg0'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "1.009 ns" { clk lightY[1]~reg0 } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk lightY[1]~reg0 } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 lightY[1]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.139 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 13 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 13; CLK Node = 'clk'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns state.D 2 REG LC_X17_Y13_N3 4 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y13_N3; Fanout = 4; REG Node = 'state.D'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "1.009 ns" { clk state.D } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk state.D } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 state.D } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk lightY[1]~reg0 } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 lightY[1]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } } { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk state.D } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 state.D } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "0.895 ns" { state.D lightY[1]~reg0 } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "0.895 ns" { state.D lightY[1]~reg0 } { 0.000ns 0.428ns } { 0.000ns 0.467ns } } } { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk lightY[1]~reg0 } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 lightY[1]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } } { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk state.D } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 state.D } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { lightY[1]~reg0 } "NODE_NAME" } } { "e:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus60/win/Technology_Viewer.qrui" "" { lightY[1]~reg0 } {  } {  } } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}