traffic.fit.qmsg

１．设计目的 （１）设计交通灯控制器； （２）学习状态机的设计方法； （３）学习原理图、状态机等多种的设计方法进行混合设计； （４）熟练掌握器件设计输入、编译、仿真和编程的过程。 ２．设计内

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "13 unused 3.30 1 12 0 " "Info: Number of I/O pins in group: 13 (unused VREF, 3.30 VCCIO, 1 input, 12 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 11 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 17 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 17 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 17 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.870 ns register register " "Info: Estimated most critical path is register to register delay of 0.870 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.C 1 REG LAB_X17_Y13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y13; Fanout = 4; REG Node = 'state.C'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { state.C } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.403 ns) + CELL(0.467 ns) 0.870 ns lightG\[3\]~reg0 2 REG LAB_X16_Y13 2 " "Info: 2: + IC(0.403 ns) + CELL(0.467 ns) = 0.870 ns; Loc. = LAB_X16_Y13; Fanout = 2; REG Node = 'lightG\[3\]~reg0'" {  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "0.870 ns" { state.C lightG[3]~reg0 } "NODE_NAME" } } { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.467 ns ( 53.68 % ) " "Info: Total cell delay = 0.467 ns ( 53.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.403 ns ( 46.32 % ) " "Info: Total interconnect delay = 0.403 ns ( 46.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "0.870 ns" { state.C lightG[3]~reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "2 " "Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "lightY\[2\] GND " "Info: Pin lightY\[2\] has GND driving its datain port" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } } { "e:/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/quartus60/win/Assignment Editor.qase" 1 { { 0 "lightY\[2\]" } } } } { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { lightY[2] } "NODE_NAME" } } { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { lightY[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "lightY\[3\] GND " "Info: Pin lightY\[3\] has GND driving its datain port" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 15 -1 0 } } { "e:/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/quartus60/win/Assignment Editor.qase" 1 { { 0 "lightY\[3\]" } } } } { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { lightY[3] } "NODE_NAME" } } { "e:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus60/win/TimingClosureFloorplan.fld" "" "" { lightY[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 02 11:39:24 2008 " "Info: Processing ended: Wed Jan 02 11:39:24 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/traffic/traffic.fit.smsg " "Info: Generated suppressed messages file E:/traffic/traffic.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}