traffic.tan.rpt

１．设计目的 （１）设计交通灯控制器； （２）学习状态机的设计方法； （３）学习原理图、状态机等多种的设计方法进行混合设计； （４）熟练掌握器件设计输入、编译、仿真和编程的过程。 ２．设计内

; N/A   ; None         ; 3.688 ns   ; esp  ; state.IDLE     ; clk      ;
; N/A   ; None         ; 3.688 ns   ; esp  ; state.G        ; clk      ;
; N/A   ; None         ; 3.688 ns   ; esp  ; state.A        ; clk      ;
; N/A   ; None         ; 3.612 ns   ; esp  ; state.B        ; clk      ;
; N/A   ; None         ; 3.612 ns   ; esp  ; state.F        ; clk      ;
; N/A   ; None         ; 3.554 ns   ; esp  ; lightR[2]~reg0 ; clk      ;
; N/A   ; None         ; 3.552 ns   ; esp  ; lightR[1]~reg0 ; clk      ;
; N/A   ; None         ; 3.552 ns   ; esp  ; lightG[1]~reg0 ; clk      ;
; N/A   ; None         ; 3.480 ns   ; esp  ; lightG[3]~reg0 ; clk      ;
; N/A   ; None         ; 3.276 ns   ; esp  ; lightY[1]~reg0 ; clk      ;
+-------+--------------+------------+------+----------------+----------+


+-----------------------------------------------------------------------------+
; tco                                                                         ;
+-------+--------------+------------+----------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From           ; To        ; From Clock ;
+-------+--------------+------------+----------------+-----------+------------+
; N/A   ; None         ; 5.756 ns   ; lightG[1]~reg0 ; lightG[1] ; clk        ;
; N/A   ; None         ; 5.524 ns   ; lightY[1]~reg0 ; lightY[1] ; clk        ;
; N/A   ; None         ; 5.524 ns   ; lightY[1]~reg0 ; lightY[0] ; clk        ;
; N/A   ; None         ; 5.515 ns   ; lightG[1]~reg0 ; lightG[0] ; clk        ;
; N/A   ; None         ; 5.274 ns   ; lightG[3]~reg0 ; lightG[3] ; clk        ;
; N/A   ; None         ; 5.182 ns   ; lightR[2]~reg0 ; lightR[2] ; clk        ;
; N/A   ; None         ; 5.182 ns   ; lightR[1]~reg0 ; lightR[1] ; clk        ;
; N/A   ; None         ; 5.182 ns   ; lightR[1]~reg0 ; lightR[0] ; clk        ;
; N/A   ; None         ; 4.937 ns   ; lightG[3]~reg0 ; lightG[2] ; clk        ;
; N/A   ; None         ; 4.935 ns   ; lightR[2]~reg0 ; lightR[3] ; clk        ;
+-------+--------------+------------+----------------+-----------+------------+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+------+----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To             ; To Clock ;
+---------------+-------------+-----------+------+----------------+----------+
; N/A           ; None        ; -3.235 ns ; esp  ; lightY[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.439 ns ; esp  ; lightG[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.511 ns ; esp  ; lightR[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.511 ns ; esp  ; lightG[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.513 ns ; esp  ; lightR[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.571 ns ; esp  ; state.B        ; clk      ;
; N/A           ; None        ; -3.571 ns ; esp  ; state.F        ; clk      ;
; N/A           ; None        ; -3.647 ns ; esp  ; state.D        ; clk      ;
; N/A           ; None        ; -3.647 ns ; esp  ; state.C        ; clk      ;
; N/A           ; None        ; -3.647 ns ; esp  ; state.E        ; clk      ;
; N/A           ; None        ; -3.647 ns ; esp  ; state.IDLE     ; clk      ;
; N/A           ; None        ; -3.647 ns ; esp  ; state.G        ; clk      ;
; N/A           ; None        ; -3.647 ns ; esp  ; state.A        ; clk      ;
+---------------+-------------+-----------+------+----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1.18 SJ Full Version
    Info: Processing started: Wed Jan 02 11:39:29 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off traffic -c traffic --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 405.19 MHz between source register "state.D" and destination register "lightY[1]~reg0"
    Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.895 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y13_N3; Fanout = 4; REG Node = 'state.D'
            Info: 2: + IC(0.428 ns) + CELL(0.467 ns) = 0.895 ns; Loc. = LC_X17_Y13_N7; Fanout = 2; REG Node = 'lightY[1]~reg0'
            Info: Total cell delay = 0.467 ns ( 52.18 % )
            Info: Total interconnect delay = 0.428 ns ( 47.82 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.139 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 13; CLK Node = 'clk'
                Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y13_N7; Fanout = 2; REG Node = 'lightY[1]~reg0'
                Info: Total cell delay = 1.677 ns ( 78.40 % )
                Info: Total interconnect delay = 0.462 ns ( 21.60 % )
            Info: - Longest clock path from clock "clk" to source register is 2.139 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 13; CLK Node = 'clk'
                Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y13_N3; Fanout = 4; REG Node = 'state.D'
                Info: Total cell delay = 1.677 ns ( 78.40 % )
                Info: Total interconnect delay = 0.462 ns ( 21.60 % )
        Info: + Micro clock to output delay of source is 0.173 ns
        Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "state.D" (data pin = "esp", clock pin = "clk") is 3.688 ns
    Info: + Longest pin to register delay is 5.798 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_88; Fanout = 13; PIN Node = 'esp'
        Info: 2: + IC(3.996 ns) + CELL(0.667 ns) = 5.798 ns; Loc. = LC_X17_Y13_N3; Fanout = 4; REG Node = 'state.D'
        Info: Total cell delay = 1.802 ns ( 31.08 % )
        Info: Total interconnect delay = 3.996 ns ( 68.92 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.139 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 13; CLK Node = 'clk'
        Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y13_N3; Fanout = 4; REG Node = 'state.D'
        Info: Total cell delay = 1.677 ns ( 78.40 % )
        Info: Total interconnect delay = 0.462 ns ( 21.60 % )
Info: tco from clock "clk" to destination pin "lightG[1]" through register "lightG[1]~reg0" is 5.756 ns
    Info: + Longest clock path from clock "clk" to source register is 2.139 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 13; CLK Node = 'clk'
        Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y13_N9; Fanout = 2; REG Node = 'lightG[1]~reg0'
        Info: Total cell delay = 1.677 ns ( 78.40 % )
        Info: Total interconnect delay = 0.462 ns ( 21.60 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 3.444 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y13_N9; Fanout = 2; REG Node = 'lightG[1]~reg0'
        Info: 2: + IC(1.822 ns) + CELL(1.622 ns) = 3.444 ns; Loc. = PIN_91; Fanout = 0; PIN Node = 'lightG[1]'
        Info: Total cell delay = 1.622 ns ( 47.10 % )
        Info: Total interconnect delay = 1.822 ns ( 52.90 % )
Info: th for register "lightY[1]~reg0" (data pin = "esp", clock pin = "clk") is -3.235 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.139 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 13; CLK Node = 'clk'
        Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y13_N7; Fanout = 2; REG Node = 'lightY[1]~reg0'
        Info: Total cell delay = 1.677 ns ( 78.40 % )
        Info: Total interconnect delay = 0.462 ns ( 21.60 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 5.386 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_88; Fanout = 13; PIN Node = 'esp'
        Info: 2: + IC(3.883 ns) + CELL(0.368 ns) = 5.386 ns; Loc. = LC_X17_Y13_N7; Fanout = 2; REG Node = 'lightY[1]~reg0'
        Info: Total cell delay = 1.503 ns ( 27.91 % )
        Info: Total interconnect delay = 3.883 ns ( 72.09 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jan 02 11:39:29 2008
    Info: Elapsed time: 00:00:01