📄 traffic.tan.rpt
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Timing Analyzer report for traffic
Wed Jan 02 11:39:29 2008
Version 6.0 Build 202 06/20/2006 Service Pack 1.18 SJ Full Version
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+----------------+----------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+----------------+----------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 3.688 ns ; esp ; state.A ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 5.756 ns ; lightG[1]~reg0 ; lightG[1] ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -3.235 ns ; esp ; lightY[1]~reg0 ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.D ; lightY[1]~reg0 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+----------------+----------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T100C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.D ; lightY[1]~reg0 ; clk ; clk ; None ; None ; 0.895 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.D ; lightG[1]~reg0 ; clk ; clk ; None ; None ; 0.894 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.A ; lightR[2]~reg0 ; clk ; clk ; None ; None ; 0.877 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.E ; lightR[1]~reg0 ; clk ; clk ; None ; None ; 0.875 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.B ; lightG[3]~reg0 ; clk ; clk ; None ; None ; 0.849 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.C ; lightG[3]~reg0 ; clk ; clk ; None ; None ; 0.802 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.C ; lightR[1]~reg0 ; clk ; clk ; None ; None ; 0.801 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.C ; lightG[1]~reg0 ; clk ; clk ; None ; None ; 0.800 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.G ; state.A ; clk ; clk ; None ; None ; 0.792 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.G ; lightR[2]~reg0 ; clk ; clk ; None ; None ; 0.789 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.F ; lightG[3]~reg0 ; clk ; clk ; None ; None ; 0.785 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.F ; state.G ; clk ; clk ; None ; None ; 0.708 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.E ; state.F ; clk ; clk ; None ; None ; 0.684 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.D ; lightR[1]~reg0 ; clk ; clk ; None ; None ; 0.678 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.D ; state.E ; clk ; clk ; None ; None ; 0.678 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.IDLE ; lightR[2]~reg0 ; clk ; clk ; None ; None ; 0.676 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.IDLE ; lightG[1]~reg0 ; clk ; clk ; None ; None ; 0.674 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.A ; state.B ; clk ; clk ; None ; None ; 0.673 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.B ; state.C ; clk ; clk ; None ; None ; 0.671 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.IDLE ; state.A ; clk ; clk ; None ; None ; 0.671 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.IDLE ; lightY[1]~reg0 ; clk ; clk ; None ; None ; 0.671 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state.C ; state.D ; clk ; clk ; None ; None ; 0.522 ns ;
+-------+------------------------------------------------+------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+----------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+----------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+----------------+----------+
; N/A ; None ; 3.688 ns ; esp ; state.D ; clk ;
; N/A ; None ; 3.688 ns ; esp ; state.C ; clk ;
; N/A ; None ; 3.688 ns ; esp ; state.E ; clk ;
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