twenty.vhd

来自「一个很好的VHDL程序.可以实现64HZ分为0.05HZ」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity twenty is
port(clk :in std_logic;
     t20_en :in std_logic;
     t20:out std_logic
     );
end entity twenty;
architecture four of twenty is
signal num : integer range 1280 downto 0:=0;
begin
process(clk,t20_en)
begin 
if(t20_en='1') then 
     if clk'event and clk='1' then 
        if num=1279 then num<=0;
         else num<=num+1;
end if;
end if;
end if;
if t20_en='0' then num<=0;
end if ;
end process;
process(clk)
begin
if clk'event and clk='1' then
     if(num=1279) then t20<='1';
     else t20<='0';
end if;
end if;
end process;
end architecture four;