📄 twenty.tan.rpt
字号:
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[6] ; clk ; clk ; None ; None ; 3.026 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[10] ; clk ; clk ; None ; None ; 2.984 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[7] ; clk ; clk ; None ; None ; 2.965 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[9] ; clk ; clk ; None ; None ; 2.963 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[5] ; clk ; clk ; None ; None ; 2.948 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[9] ; num[10] ; clk ; clk ; None ; None ; 2.945 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[6] ; clk ; clk ; None ; None ; 2.940 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; t20~reg0 ; clk ; clk ; None ; None ; 2.923 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[8] ; num[10] ; clk ; clk ; None ; None ; 2.913 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[8] ; clk ; clk ; None ; None ; 2.905 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[7] ; clk ; clk ; None ; None ; 2.897 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[8] ; num[9] ; clk ; clk ; None ; None ; 2.895 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; t20~reg0 ; clk ; clk ; None ; None ; 2.887 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[7] ; clk ; clk ; None ; None ; 2.882 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; t20~reg0 ; clk ; clk ; None ; None ; 2.757 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[5] ; clk ; clk ; None ; None ; 2.711 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[6] ; num[7] ; clk ; clk ; None ; None ; 2.710 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[6] ; clk ; clk ; None ; None ; 2.703 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[5] ; clk ; clk ; None ; None ; 2.643 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[6] ; clk ; clk ; None ; None ; 2.635 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[5] ; clk ; clk ; None ; None ; 2.628 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[6] ; clk ; clk ; None ; None ; 2.620 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[7] ; clk ; clk ; None ; None ; 2.617 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[10] ; num[10] ; clk ; clk ; None ; None ; 2.596 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[10] ; num[8] ; clk ; clk ; None ; None ; 2.595 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[1] ; clk ; clk ; None ; None ; 2.545 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[4] ; clk ; clk ; None ; None ; 2.526 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[3] ; clk ; clk ; None ; None ; 2.453 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; t20~reg0 ; clk ; clk ; None ; None ; 2.450 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[4] ; clk ; clk ; None ; None ; 2.440 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[3] ; clk ; clk ; None ; None ; 2.367 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[2] ; clk ; clk ; None ; None ; 2.366 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[8] ; num[8] ; clk ; clk ; None ; None ; 2.349 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[9] ; num[9] ; clk ; clk ; None ; None ; 2.345 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[7] ; num[7] ; clk ; clk ; None ; None ; 2.330 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[2] ; clk ; clk ; None ; None ; 2.280 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[6] ; clk ; clk ; None ; None ; 2.275 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[4] ; clk ; clk ; None ; None ; 2.201 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; t20~reg0 ; clk ; clk ; None ; None ; 2.175 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[4] ; clk ; clk ; None ; None ; 2.131 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[3] ; clk ; clk ; None ; None ; 2.128 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[9] ; num[8] ; clk ; clk ; None ; None ; 2.120 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[1] ; clk ; clk ; None ; None ; 1.946 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; t20~reg0 ; clk ; clk ; None ; None ; 1.895 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[0] ; clk ; clk ; None ; None ; 1.877 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[6] ; num[6] ; clk ; clk ; None ; None ; 1.855 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[10] ; t20~reg0 ; clk ; clk ; None ; None ; 1.768 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[5] ; clk ; clk ; None ; None ; 1.685 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[3] ; clk ; clk ; None ; None ; 1.540 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[2] ; clk ; clk ; None ; None ; 1.523 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[4] ; clk ; clk ; None ; None ; 1.520 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[8] ; t20~reg0 ; clk ; clk ; None ; None ; 1.484 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[9] ; t20~reg0 ; clk ; clk ; None ; None ; 1.293 ns ;
+-------+------------------------------------------------+---------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+----------+-----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+----------+-----+------------+
; N/A ; None ; 7.849 ns ; t20~reg0 ; t20 ; clk ;
+-------+--------------+------------+----------+-----+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Mon Dec 31 23:19:58 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off twenty -c twenty --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 224.87 MHz between source register "num[7]" and destination register "num[10]" (period= 4.447 ns)
Info: + Longest register to register delay is 4.186 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y11_N2; Fanout = 4; REG Node = 'num[7]'
Info: 2: + IC(1.260 ns) + CELL(0.590 ns) = 1.850 ns; Loc. = LC_X10_Y12_N3; Fanout = 2; COMB Node = 'Equal0~99'
Info: 3: + IC(1.208 ns) + CELL(0.114 ns) = 3.172 ns; Loc. = LC_X9_Y11_N9; Fanout = 2; COMB Node = 'Equal0~101'
Info: 4: + IC(0.705 ns) + CELL(0.309 ns) = 4.186 ns; Loc. = LC_X10_Y11_N9; Fanout = 2; REG Node = 'num[10]'
Info: Total cell delay = 1.013 ns ( 24.20 % )
Info: Total interconnect delay = 3.173 ns ( 75.80 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.925 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 12; CLK Node = 'clk'
Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X10_Y11_N9; Fanout = 2; REG Node = 'num[10]'
Info: Total cell delay = 2.180 ns ( 74.53 % )
Info: Total interconnect delay = 0.745 ns ( 25.47 % )
Info: - Longest clock path from clock "clk" to source register is 2.925 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 12; CLK Node = 'clk'
Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X11_Y11_N2; Fanout = 4; REG Node = 'num[7]'
Info: Total cell delay = 2.180 ns ( 74.53 % )
Info: Total interconnect delay = 0.745 ns ( 25.47 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "t20" through register "t20~reg0" is 7.849 ns
Info: + Longest clock path from clock "clk" to source register is 2.925 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 12; CLK Node = 'clk'
Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X9_Y11_N9; Fanout = 1; REG Node = 't20~reg0'
Info: Total cell delay = 2.180 ns ( 74.53 % )
Info: Total interconnect delay = 0.745 ns ( 25.47 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 4.700 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y11_N9; Fanout = 1; REG Node = 't20~reg0'
Info: 2: + IC(2.592 ns) + CELL(2.108 ns) = 4.700 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 't20'
Info: Total cell delay = 2.108 ns ( 44.85 % )
Info: Total interconnect delay = 2.592 ns ( 55.15 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Mon Dec 31 23:19:59 2007
Info: Elapsed time: 00:00:01
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