📄 twenty.tan.rpt
字号:
Timing Analyzer report for twenty
Mon Dec 31 23:19:59 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+----------+---------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------+---------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 7.849 ns ; t20~reg0 ; t20 ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 224.87 MHz ( period = 4.447 ns ) ; num[7] ; num[10] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+----------+---------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+---------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 224.87 MHz ( period = 4.447 ns ) ; num[7] ; num[10] ; clk ; clk ; None ; None ; 4.186 ns ;
; N/A ; 224.92 MHz ( period = 4.446 ns ) ; num[7] ; num[8] ; clk ; clk ; None ; None ; 4.185 ns ;
; N/A ; 234.30 MHz ( period = 4.268 ns ) ; num[6] ; num[10] ; clk ; clk ; None ; None ; 4.007 ns ;
; N/A ; 234.36 MHz ( period = 4.267 ns ) ; num[6] ; num[8] ; clk ; clk ; None ; None ; 4.006 ns ;
; N/A ; 247.95 MHz ( period = 4.033 ns ) ; num[0] ; num[10] ; clk ; clk ; None ; None ; 3.772 ns ;
; N/A ; 248.02 MHz ( period = 4.032 ns ) ; num[0] ; num[8] ; clk ; clk ; None ; None ; 3.771 ns ;
; N/A ; 252.08 MHz ( period = 3.967 ns ) ; num[5] ; num[10] ; clk ; clk ; None ; None ; 3.706 ns ;
; N/A ; 252.14 MHz ( period = 3.966 ns ) ; num[5] ; num[8] ; clk ; clk ; None ; None ; 3.705 ns ;
; N/A ; 258.60 MHz ( period = 3.867 ns ) ; num[2] ; num[10] ; clk ; clk ; None ; None ; 3.606 ns ;
; N/A ; 258.67 MHz ( period = 3.866 ns ) ; num[2] ; num[8] ; clk ; clk ; None ; None ; 3.605 ns ;
; N/A ; 267.74 MHz ( period = 3.735 ns ) ; num[0] ; num[9] ; clk ; clk ; None ; None ; 3.474 ns ;
; N/A ; 274.05 MHz ( period = 3.649 ns ) ; num[1] ; num[9] ; clk ; clk ; None ; None ; 3.388 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[7] ; t20~reg0 ; clk ; clk ; None ; None ; 3.367 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[10] ; clk ; clk ; None ; None ; 3.304 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[10] ; clk ; clk ; None ; None ; 3.299 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[8] ; clk ; clk ; None ; None ; 3.298 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[7] ; clk ; clk ; None ; None ; 3.288 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[8] ; clk ; clk ; None ; None ; 3.225 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[7] ; clk ; clk ; None ; None ; 3.202 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[7] ; num[9] ; clk ; clk ; None ; None ; 3.189 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[6] ; t20~reg0 ; clk ; clk ; None ; None ; 3.188 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[9] ; clk ; clk ; None ; None ; 3.151 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[9] ; clk ; clk ; None ; None ; 3.083 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[9] ; clk ; clk ; None ; None ; 3.068 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[6] ; num[9] ; clk ; clk ; None ; None ; 3.056 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[5] ; clk ; clk ; None ; None ; 3.034 ns ;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -