twenty.tan.summary

一个很好的VHDL程序.可以实现64HZ分为0.05HZ

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.849 ns
From           : t20~reg0
To             : t20
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 224.87 MHz ( period = 4.447 ns )
From           : num[7]
To             : num[10]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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