ten.map.summary

来自「一个很好的VHDL程序.可以实现64HZ分为0.1HZ」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Mon Dec 31 21:40:57 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : ten
Top-level Entity Name : ten
Family : Cyclone
Total logic elements : 25
Total pins : 3
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0