📄 ten.tan.rpt
字号:
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[6] ; clk ; clk ; None ; None ; 3.036 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[9] ; clk ; clk ; None ; None ; 3.034 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[6] ; num[8] ; clk ; clk ; None ; None ; 3.019 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[4] ; clk ; clk ; None ; None ; 3.012 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[7] ; clk ; clk ; None ; None ; 3.011 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[7] ; num[9] ; clk ; clk ; None ; None ; 3.010 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[8] ; clk ; clk ; None ; None ; 2.958 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[7] ; clk ; clk ; None ; None ; 2.951 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[9] ; clk ; clk ; None ; None ; 2.949 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[8] ; clk ; clk ; None ; None ; 2.949 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[7] ; clk ; clk ; None ; None ; 2.948 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[6] ; clk ; clk ; None ; None ; 2.947 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[9] ; clk ; clk ; None ; None ; 2.945 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[7] ; num[8] ; clk ; clk ; None ; None ; 2.943 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[6] ; clk ; clk ; None ; None ; 2.938 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[4] ; clk ; clk ; None ; None ; 2.931 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[6] ; clk ; clk ; None ; None ; 2.930 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[4] ; clk ; clk ; None ; None ; 2.858 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[2] ; clk ; clk ; None ; None ; 2.851 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[8] ; num[9] ; clk ; clk ; None ; None ; 2.783 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[2] ; clk ; clk ; None ; None ; 2.770 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[4] ; clk ; clk ; None ; None ; 2.767 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[1] ; clk ; clk ; None ; None ; 2.764 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[5] ; clk ; clk ; None ; None ; 2.625 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[3] ; clk ; clk ; None ; None ; 2.604 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[7] ; num[7] ; clk ; clk ; None ; None ; 2.504 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[8] ; num[7] ; clk ; clk ; None ; None ; 2.500 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[0] ; clk ; clk ; None ; None ; 2.453 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[6] ; num[6] ; clk ; clk ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; t10~reg0 ; clk ; clk ; None ; None ; 2.236 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[8] ; num[8] ; clk ; clk ; None ; None ; 2.198 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[6] ; t10~reg0 ; clk ; clk ; None ; None ; 2.192 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[2] ; clk ; clk ; None ; None ; 2.179 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[4] ; clk ; clk ; None ; None ; 2.178 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[1] ; clk ; clk ; None ; None ; 2.165 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[9] ; num[7] ; clk ; clk ; None ; None ; 2.146 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[9] ; num[9] ; clk ; clk ; None ; None ; 2.144 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; t10~reg0 ; clk ; clk ; None ; None ; 2.134 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; t10~reg0 ; clk ; clk ; None ; None ; 2.131 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; t10~reg0 ; clk ; clk ; None ; None ; 2.089 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[8] ; t10~reg0 ; clk ; clk ; None ; None ; 1.659 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[7] ; t10~reg0 ; clk ; clk ; None ; None ; 1.642 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; t10~reg0 ; clk ; clk ; None ; None ; 1.335 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[9] ; t10~reg0 ; clk ; clk ; None ; None ; 1.267 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; t10~reg0 ; clk ; clk ; None ; None ; 1.131 ns ;
+-------+------------------------------------------------+--------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+----------+-----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+----------+-----+------------+
; N/A ; None ; 7.574 ns ; t10~reg0 ; t10 ; clk ;
+-------+--------------+------------+----------+-----+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Mon Dec 31 21:41:06 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ten -c ten --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 267.74 MHz between source register "num[0]" and destination register "num[5]" (period= 3.735 ns)
Info: + Longest register to register delay is 3.474 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y11_N9; Fanout = 4; REG Node = 'num[0]'
Info: 2: + IC(0.730 ns) + CELL(0.423 ns) = 1.153 ns; Loc. = LC_X14_Y11_N0; Fanout = 2; COMB Node = 'Add0~150'
Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.231 ns; Loc. = LC_X14_Y11_N1; Fanout = 2; COMB Node = 'Add0~148'
Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.309 ns; Loc. = LC_X14_Y11_N2; Fanout = 2; COMB Node = 'Add0~152'
Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 1.387 ns; Loc. = LC_X14_Y11_N3; Fanout = 2; COMB Node = 'Add0~154'
Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 1.565 ns; Loc. = LC_X14_Y11_N4; Fanout = 5; COMB Node = 'Add0~156'
Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.186 ns; Loc. = LC_X14_Y11_N5; Fanout = 1; COMB Node = 'Add0~157'
Info: 8: + IC(0.681 ns) + CELL(0.607 ns) = 3.474 ns; Loc. = LC_X15_Y11_N2; Fanout = 4; REG Node = 'num[5]'
Info: Total cell delay = 2.063 ns ( 59.38 % )
Info: Total interconnect delay = 1.411 ns ( 40.62 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.925 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 11; CLK Node = 'clk'
Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X15_Y11_N2; Fanout = 4; REG Node = 'num[5]'
Info: Total cell delay = 2.180 ns ( 74.53 % )
Info: Total interconnect delay = 0.745 ns ( 25.47 % )
Info: - Longest clock path from clock "clk" to source register is 2.925 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 11; CLK Node = 'clk'
Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X13_Y11_N9; Fanout = 4; REG Node = 'num[0]'
Info: Total cell delay = 2.180 ns ( 74.53 % )
Info: Total interconnect delay = 0.745 ns ( 25.47 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "t10" through register "t10~reg0" is 7.574 ns
Info: + Longest clock path from clock "clk" to source register is 2.925 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 11; CLK Node = 'clk'
Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X15_Y11_N8; Fanout = 1; REG Node = 't10~reg0'
Info: Total cell delay = 2.180 ns ( 74.53 % )
Info: Total interconnect delay = 0.745 ns ( 25.47 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 4.425 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y11_N8; Fanout = 1; REG Node = 't10~reg0'
Info: 2: + IC(2.317 ns) + CELL(2.108 ns) = 4.425 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 't10'
Info: Total cell delay = 2.108 ns ( 47.64 % )
Info: Total interconnect delay = 2.317 ns ( 52.36 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Mon Dec 31 21:41:06 2007
Info: Elapsed time: 00:00:01
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