ten.tan.rpt

一个很好的VHDL程序.可以实现64HZ分为0.1HZ

Timing Analyzer report for ten
Mon Dec 31 21:41:06 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                            ;
+------------------------------+-------+---------------+----------------------------------+----------+--------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From     ; To     ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------+--------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 7.574 ns                         ; t10~reg0 ; t10    ; clk        ; --       ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 267.74 MHz ( period = 3.735 ns ) ; num[0]   ; num[5] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;          ;        ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+----------+--------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                     ;
+-------+------------------------------------------------+--------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From   ; To       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 267.74 MHz ( period = 3.735 ns )               ; num[0] ; num[5]   ; clk        ; clk      ; None                        ; None                      ; 3.474 ns                ;
; N/A   ; 273.52 MHz ( period = 3.656 ns )               ; num[1] ; num[5]   ; clk        ; clk      ; None                        ; None                      ; 3.395 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[3]   ; clk        ; clk      ; None                        ; None                      ; 3.367 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[5]   ; clk        ; clk      ; None                        ; None                      ; 3.324 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[3]   ; clk        ; clk      ; None                        ; None                      ; 3.286 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[5]   ; clk        ; clk      ; None                        ; None                      ; 3.235 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[5]   ; clk        ; clk      ; None                        ; None                      ; 3.226 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[3]   ; clk        ; clk      ; None                        ; None                      ; 3.213 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[8]   ; clk        ; clk      ; None                        ; None                      ; 3.197 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[7]   ; clk        ; clk      ; None                        ; None                      ; 3.187 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[6]   ; clk        ; clk      ; None                        ; None                      ; 3.186 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[9]   ; clk        ; clk      ; None                        ; None                      ; 3.184 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[9]   ; clk        ; clk      ; None                        ; None                      ; 3.168 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[8]   ; clk        ; clk      ; None                        ; None                      ; 3.118 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[7]   ; clk        ; clk      ; None                        ; None                      ; 3.108 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[6]   ; clk        ; clk      ; None                        ; None                      ; 3.107 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[9]   ; clk        ; clk      ; None                        ; None                      ; 3.105 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[8]   ; clk        ; clk      ; None                        ; None                      ; 3.101 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[6] ; num[9]   ; clk        ; clk      ; None                        ; None                      ; 3.086 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[6] ; num[7]   ; clk        ; clk      ; None                        ; None                      ; 3.054 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[8]   ; clk        ; clk      ; None                        ; None                      ; 3.047 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[7]   ; clk        ; clk      ; None                        ; None                      ; 3.037 ns                ;