cnt10.vhd

来自「基于vhdl的10进制计数器模块」· VHDL 代码 · 共 31 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt10 IS
PORT (rst,en,clk:IN STD_LOGIC;
cout:OUT STD_LOGIC;
cq:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END CNT10;
ARCHITECTURE behav OF cnt10 IS
BEGIN
PROCESS(clk,rst,en)
variable cqi:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF rst ='1' THEN 
cqi:=(others=>'0');
ELSIF clk'event and clk='1' THEN
IF(en='1') THEN
IF(cqi<9) THEN
cqi := cqi+1;
ELSE cqi:= (others=>'0');
END IF;
END IF;
END IF;
IF cqi=9 then cout<='1';
Else cout<='0';
END IF;
Cq<=cqi;
END PROCESS;
END behav;