cnt6.vhd

基于vhdl的6进制计数器模块

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt6 IS
PORT (rst,en,clk:IN STD_LOGIC;
cout:OUT STD_LOGIC;
cq:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END CNT6;
ARCHITECTURE behav OF cnt6 IS
BEGIN
PROCESS(clk,rst,en)
variable cqi:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF rst ='1' THEN 
cqi:=(others=>'0');
ELSIF clk'event and clk='1' THEN
IF(en='1') THEN
IF(cqi<5) THEN
cqi := cqi+1;
ELSE cqi:= (others=>'0');
END IF;
END IF;
END IF;
IF cqi=5 then cout<='1';
Else cout<='0';
END IF;
Cq<=cqi;
END PROCESS;
END behav;