bmq1.vhd

VHDL的课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bmq1 is
port(en,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9    :in  std_logic;
       sor         :out   std_logic;
      y           :out   std_logic_vector(3 downto 0));
     
end bmq1;
architecture behav of bmq1 is
begin
process(en,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9)
begin
if(en='1')then
if(s9='1')then
y<="1001";sor<='1';
elsif(s8='1')then
y<="1000";sor<='1';
elsif(s7='1')then
y<="0111";sor<='1';
elsif(s6='1')then
y<="0110";sor<='1';
elsif(s5='1')then
y<="0101";sor<='1';
elsif(s4='1')then
y<="0100";sor<='1';
elsif(s3='1')then
y<="0011";sor<='1';
elsif(s2='1')then
y<="0010";sor<='1';
elsif(s1='1')then
y<="0001";sor<='1';
elsif(s0='1')then
y<="0000";sor<='1';
else y<="1111";sor<='0';
end if;
end if;
end process;
end behav;