📄 routed.par
字号:
Release 9.1.03i par J.33Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.XCOJAMESM20:: Thu Apr 19 15:39:25 2007par -ol high -w mapped.ncd routed.ncd mapped.pcf Constraints file: mapped.pcf.Loading device for application Rf_Device from file '5vlx50t.nph' in environment C:\XILINX_91i_J.33.10_SP3. "xilinx_pci_exp_1_lane_ep" is an NCD, version 3.1, device xc5vlx50t, package ff1136, speed -1The STEPPING level for this design is ES.Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)Device speed data version: "ADVANCED 1.53 2007-03-08".INFO:Par:253 - The Map -timing placement will be retained since it is likely to achieve better performance.Device Utilization Summary: Number of BUFDSs 1 out of 6 16% Number of BUFGs 4 out of 32 12% Number of GTP_DUALs 1 out of 6 16% Number of LOCed GTP_DUALs 1 out of 1 100% Number of External IOBs 1 out of 480 1% Number of LOCed IOBs 1 out of 1 100% Number of External IPADs 4 out of 518 1% Number of LOCed IPADs 2 out of 4 50% Number of External OPADs 2 out of 24 8% Number of LOCed OPADs 0 out of 2 0% Number of PCIEs 1 out of 1 100% Number of PLL_ADVs 1 out of 6 16% Number of RAMB36SDP_EXPs 2 out of 60 3% Number of LOCed RAMB36SDP_EXPs 1 out of 2 50% Number of RAMB36_EXPs 8 out of 60 13% Number of LOCed RAMB36_EXPs 4 out of 8 50% Number of Slice Registers 2195 out of 28800 7% Number used as Flip Flops 2194 Number used as Latches 1 Number used as LatchThrus 0 Number of Slice LUTS 1953 out of 28800 6% Number of Slice LUT-Flip Flop pairs 2735 out of 28800 9%Overall effort level (-ol): High Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 26 secs Finished initial Timing Analysis. REAL time: 26 secs Starting RouterPhase 1: 16092 unrouted; REAL time: 28 secs Phase 2: 13297 unrouted; REAL time: 30 secs Phase 3: 5208 unrouted; REAL time: 43 secs Phase 4: 5208 unrouted; (16263) REAL time: 44 secs Phase 5: 5254 unrouted; (10466) REAL time: 1 mins 12 secs Phase 6: 5254 unrouted; (10466) REAL time: 1 mins 12 secs Phase 7: 0 unrouted; (8780) REAL time: 1 mins 42 secs Phase 8: 0 unrouted; (8780) REAL time: 2 mins 2 secs Updating file: routed.ncd with current fully routed design.Phase 9: 0 unrouted; (8780) REAL time: 2 mins 11 secs Phase 10: 0 unrouted; (8780) REAL time: 2 mins 13 secs Phase 11: 0 unrouted; (0) REAL time: 2 mins 15 secs Total REAL time to Router completion: 2 mins 15 secs Total CPU time to Router completion: 2 mins 12 secs Partition Implementation Status------------------------------- No Partitions were found in this design.-------------------------------Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+| trn_clk_c | BUFGCTRL_X0Y4| No | 1096 | 0.439 | 1.944 |+---------------------+--------------+------+------+------------+-------------+|ep/BU2/U0/pcie_ep0/p | | | | | || cie_blk/core_clk |BUFGCTRL_X0Y14| No | 62 | 0.261 | 1.808 |+---------------------+--------------+------+------+------------+-------------+|ep/BU2/U0/pcie_ep0/p | | | | | ||cie_blk/pcie_gt_wrap | | | | | || per_i/icdrreset<0> | Local| | 1 | 0.000 | 0.459 |+---------------------+--------------+------+------+------------+-------------+* Net Skew is the difference between the minimum and maximum routingonly delays for the net. Note this is different from Clock Skew whichis reported in TRCE timing report. Clock Skew is the difference betweenthe minimum and maximum path delays which includes logic delays. The Delay Summary ReportThe NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for this design is: 1.466 The MAXIMUM PIN DELAY IS: 6.859 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 5.171 Listing Pin Delays by value: (nsec) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 7.00 d >= 7.00 --------- --------- --------- --------- --------- --------- 5415 4706 2005 612 393 0Timing Score: 0Number of Timing Constraints that were not applied: 6Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation.------------------------------------------------------------------------------------------------------ Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ------------------------------------------------------------------------------------------------------ PERIOD analysis for net "ep/BU2/U0/pcie_e | SETUP | 0.001ns| 3.999ns| 0| 0 p0/pcie_blk/clocking_i/clkout0" derived f | HOLD | 0.023ns| | 0| 0 rom NET "sys_clk_c" PERIOD = 10 ns HIGH | | | | | 50% | | | | | ------------------------------------------------------------------------------------------------------ PERIOD analysis for net "ep/BU2/U0/pcie_e | SETUP | 4.572ns| 11.428ns| 0| 0 p0/pcie_blk/clocking_i/clkout1" derived f | HOLD | 0.005ns| | 0| 0 rom NET "sys_clk_c" PERIOD = 10 ns HIGH | | | | | 50% | | | | | ------------------------------------------------------------------------------------------------------ NET "sys_clk_c" PERIOD = 10 ns HIGH 50% | N/A | N/A| N/A| N/A| N/A------------------------------------------------------------------------------------------------------ PERIOD analysis for net "ep/BU2/U0/pcie_e | N/A | N/A| N/A| N/A| N/A p0/pcie_blk/clocking_i/clkout0" derived f | | | | | rom NET "sys_clk_c" PERIOD = 10 ns HIGH | | | | | 50% | | | | | ------------------------------------------------------------------------------------------------------ PERIOD analysis for net "ep/BU2/U0/pcie_e | N/A | N/A| N/A| N/A| N/A p0/pcie_blk/clocking_i/clkout1" derived f | | | | | rom NET "sys_clk_c" PERIOD = 10 ns HIGH | | | | | 50% | | | | | ------------------------------------------------------------------------------------------------------ TS_MGTCLK = PERIOD TIMEGRP "MGTCLK" 100 M | N/A | N/A| N/A| N/A| N/A Hz HIGH 50% | | | | | ------------------------------------------------------------------------------------------------------ TS_ep_BU2_U0_pcie_ep0_pcie_blk_clocking_i | N/A | N/A| N/A| N/A| N/A _clkout0 = PERIOD TIMEGRP "ep_BU2 | | | | | _U0_pcie_ep0_pcie_blk_clocking_i_clkout0" | | | | | TS_MGTCLK * 2.5 HIGH 50% | | | | | ------------------------------------------------------------------------------------------------------ TS_ep_BU2_U0_pcie_ep0_pcie_blk_clocking_i | N/A | N/A| N/A| N/A| N/A _clkout1 = PERIOD TIMEGRP "ep_BU2 | | | | | _U0_pcie_ep0_pcie_blk_clocking_i_clkout1" | | | | | TS_MGTCLK * 0.625 HIGH 50% | | | | | ------------------------------------------------------------------------------------------------------All constraints were met.INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 2 mins 19 secs Total CPU time to PAR completion: 2 mins 15 secs Peak Memory Usage: 412 MBPlacer: Placement generated during map.Routing: Completed - No errors found.Timing: Completed - No errors found.Number of error messages: 0Number of warning messages: 0Number of info messages: 1Writing design to file routed.ncdPAR done!⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -