isp.rpt

通用FPGA CPLD下载电缆的XC9536XL编译程序

    tdi.TRST  =  "N270/N270_TRST"    

 tms  =  /s0 * /s2 * pdb4
	+ /s0 * /s1 * pdb4
	+ /s2 * /s1 * pdb4
	+ s0 * /s2 * s1 * pdb3
    tms.TRST  =  "N270/N270_TRST"    

 "N270/N270_TRST"  =  s0 * /s2 * /s1
	+ s0 * /s2 * /pdb14
	+ /s0 * s2 * /s1
	+ /s0 * /s2 * /pdb5    

 tdo  =  Gnd
    tdo.TRST  =  /pdb6 * /s0 * /s2 * s1    

 ispen  =  /s0 * s2 * /s1 * /pdb5
	+ /s0 * /s2 * /s1 * pdb5
    ispen.TRST  =  /s0 * /s1    

****************************  Device Pin Out ****************************

Device : XC9536XL-5-PC44


              p  p                       
              d  d  p  p     p        p  
        T  T  b  b  d  d  t  d  T  V  d  
        I  I  1  1  b  b  d  b  I  C  b  
        E  E  0  2  9  7  i  4  E  C  2  
        --------------------------------  
       /6  5  4  3  2  1  44 43 42 41 40 \
  TIE | 7                             39 | s2
  TIE | 8                             38 | tms
pdb13 | 9                             37 | s0
  GND | 10                            36 | pdb5
  TIE | 11        XC9536XL-5-PC44     35 | pdb8
  TIE | 12                            34 | tck
  TIE | 13                            33 | s1
pdb15 | 14                            32 | VCC
  TDI | 15                            31 | GND
  TMS | 16                            30 | TDO
  TCK | 17                            29 | pdb14
      \ 18 19 20 21 22 23 24 25 26 27 28 /
        --------------------------------  
        t  T  T  V  T  G  p  T  p  i  p  
        d  I  I  C  I  N  d  I  d  s  d  
        o  E  E  C  E  D  b  E  b  p  b  
                          1     6  e  3  
                          1        n     


Legend :  NC  = Not Connected, unbonded pin
         TIE  = Tie pin to GND or board trace driven to valid logic level
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC9536XL-5-PC44
Use Timing Constraints                      : ON
Use Design Location Constraints             : ON
Create Programmable Ground Pins             : OFF
Use Advanced Fitting                        : ON
Use Local Feedback                          : OFF
Use Pin Feedback                            : OFF
Default Power Setting                       : STD
Default Output Slew Rate                    : FAST
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : OFF
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Global Clock(GCK) Optimization              : ON
Global Set/Reset(GSR) Optimization          : ON
Global Output Enable(GTS) Optimization      : ON
Collapsing pterm limit                      : 25
Collapsing input limit                      : 54

















将Abel翻译成VHDL文件如下：
--isp Download Cable
library IEEE;
use IEEE.std_logic_1164.all;
library aim;
use aim.components.all;
library pls;
use pls.attributes.all;
entity isp is
port (
    S0 : in std_logic;
    S1 : in std_logic;
    S2 : in std_logic;
    PDB14 : in std_logic;
    PDB2 : in std_logic;
    PDB3 : in std_logic;
    PDB4 : in std_logic;
    PDB5 : in std_logic;
    PDB6 : in std_logic;
    PDB7 : in std_logic;
    PDB8 : in std_logic;
    PDB9 : in std_logic;
    PDB10 : out std_logic;
    PDB11 : out std_logic;
    PDB12 : out std_logic;
    PDB13 : out std_logic;
    PDB15 : out std_logic;
    TCK : out std_logic;
    TDO : inout std_logic;
    TMS : out std_logic;
    ispEN : inout std_logic;
    TDI : out std_logic
     );
end isp;
architecture equation of isp is
    signal isp_OE1 : std_logic;
    signal isp_OE3 : std_logic;
    signal isp_OE5 : std_logic;
    signal isp_OE7 : std_logic;
    signal isp_OE9 : std_logic;
    signal PDB10_xcBUF : std_logic;
    signal PDB11_xcBUF : std_logic;
    signal PDB12_xcBUF : std_logic;
    signal PDB13_xcBUF : std_logic;
    signal PDB15_xcBUF : std_logic;
    signal TCK_xcBUF : std_logic;
    signal TCK_xcOE : std_logic;
    signal TDO_xcBUF : std_logic;
    signal TDO_xcOE : std_logic;
    signal TMS_xcBUF : std_logic;
    signal TMS_xcOE : std_logic;
    signal ispEN_xcBUF : std_logic;
    signal ispEN_xcOE : std_logic;
    signal TDI_xcBUF : std_logic;
    signal TDI_xcOE : std_logic;
    signal vcc : std_logic;
    signal gnd : std_logic;
begin
vcc <= '1';
gnd <= '0';
PDB10_xcBUF <= (( not(S0) and  not(S1) and TDO)
       or  (PDB7 and S0 and S1 and  not(S2)));
PDB10 <= (PDB10_xcBUF);
PDB11_xcBUF <= ((S0 and  not(S2) and TDO)
       or  (PDB6 and  not(S0) and  not(S1) and S2)
       or  (PDB8 and  not(S0) and S1 and  not(S2)));
PDB11 <= (PDB11_xcBUF);
PDB12_xcBUF <= (( not(S0) and  not(S1) and S2)
       or  (PDB8 and  not(S0) and  not(S2))
       or  (PDB9 and S0 and S1 and  not(S2)));
PDB12 <= (PDB12_xcBUF);
PDB13_xcBUF <= (( not(S0) and S1 and  not(S2) and TDO)
       or  (S0 and S1 and  not(S2) and ispEN));
PDB13 <= (PDB13_xcBUF);
PDB15_xcBUF <= (( not(S0) and  not(S2)));
PDB15 <= (PDB15_xcBUF);
TCK_xcOE <=  ((isp_OE1));
TCK_xcBUF <= ((PDB2 and S0 and  not(S2))
       or  (PDB3 and  not(S0) and  not(S2))
       or  (PDB2 and  not(S0) and  not(S1) and S2));
TCK <= (TCK_xcBUF) when (TCK_xcOE = '1') else 'Z';
TDO_xcOE <=  ((isp_OE3));
TDO_xcBUF <= (gnd);
TDO <= (TDO_xcBUF) when (TDO_xcOE = '1') else 'Z';
TMS_xcOE <=  ((isp_OE5));
TMS_xcBUF <= ((PDB4 and  not(S0) and  not(S1))
       or  (PDB4 and  not(S0) and  not(S2))
       or  (PDB4 and  not(S1) and  not(S2))
       or  (PDB3 and S0 and S1 and  not(S2)));
TMS <= (TMS_xcBUF) when (TMS_xcOE = '1') else 'Z';
ispEN_xcOE <=  ((isp_OE7));
ispEN_xcBUF <= (( not(PDB5) and  not(S0) and  not(S1) and S2)
       or  (PDB5 and  not(S0) and  not(S1) and  not(S2)));
ispEN <= (ispEN_xcBUF) when (ispEN_xcOE = '1') else 'Z';
TDI_xcOE <=  ((isp_OE9));
TDI_xcBUF <= ((PDB2 and  not(S0) and  not(S2))
       or  (PDB3 and  not(S0) and  not(S1) and S2)
       or  (PDB8 and S0 and S1 and  not(S2))
       or  (PDB3 and S0 and  not(S1) and  not(S2)));
TDI <= (TDI_xcBUF) when (TDI_xcOE = '1') else 'Z';
isp_OE1 <= (( not(S0) and  not(S1) and S2)
       or  ( not(PDB14) and S0 and  not(S2))
       or  ( not(PDB5) and  not(S0) and  not(S2))
       or  (S0 and  not(S1) and  not(S2)));
isp_OE3 <= (( not(PDB6) and  not(S0) and S1 and  not(S2)));
isp_OE5 <= (( not(S0) and  not(S1) and S2)
       or  ( not(PDB14) and S0 and  not(S2))
       or  ( not(PDB5) and  not(S0) and  not(S2))
       or  (S0 and  not(S1) and  not(S2)));
isp_OE7 <= (( not(S0) and  not(S1)));
isp_OE9 <= (( not(S0) and  not(S1) and S2)
       or  ( not(PDB14) and S0 and  not(S2))
       or  ( not(PDB5) and  not(S0) and  not(S2))
       or  (S0 and  not(S1) and  not(S2)));
end equation;