📄 isp.rpt
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cpldfit: version E.38 Xilinx Inc.
Fitter Report
Design Name: isp Date: 11- 3-2002, 10:33AM
Device Used: XC9536XL-5-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
11 /36 ( 30%) 33 /180 ( 18%) 0 /36 ( 0%) 22 /34 ( 64%) 20 /108 ( 18%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 12 12 | I/O : 20 8
Output : 8 8 | GCK/IO : 0 3
Bidirectional : 2 2 | GTS/IO : 1 1
GCK : 0 0 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 22 22
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 0
Non-registered Macrocell driving I/O 10
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 11 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 11 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
N270/N270_TRST 4 5 FB1_18 STD (b) (b)
ispen 3 4 FB2_15 STD FAST 27 I/O I/O
pdb10 2 5 FB1_4 STD FAST 4 I/O O
pdb11 3 6 FB1_17 STD FAST 24 I/O O
pdb12 3 5 FB1_2 STD FAST 3 I/O O
pdb13 2 5 FB1_8 STD FAST 9 I/O O
pdb15 1 2 FB1_12 STD FAST 14 I/O O
tck 4 6 FB2_11 STD FAST 34 I/O O
tdi 5 7 FB2_2 STD FAST 44 I/O O
tdo 1 4 FB1_13 STD FAST 18 I/O I/O
tms 5 6 FB2_7 STD FAST 38 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
pdb14 FB2_13 29 I/O I
pdb2 FB2_5 40 GTS/I/O I
pdb3 FB2_14 28 I/O I
pdb4 FB2_4 43 I/O I
pdb5 FB2_9 36 I/O I
pdb6 FB2_16 26 I/O I
pdb7 FB2_1 1 I/O I
pdb8 FB2_10 35 I/O I
pdb9 FB1_1 2 I/O I
s0 FB2_8 37 I/O I
s1 FB2_12 33 I/O I
s2 FB2_6 39 GSR/I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 7 11 11 16 5/1 17
FB2 4 9 9 17 3/1 17
---- ----- ----- -----
11 33 8/2 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 11/43
Number of signals used by logic mapping into function block: 11
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 2 I/O I
pdb12 3 0 0 2 FB1_2 STD 3 I/O O
(unused) 0 0 0 5 FB1_3 5 GCK/I/O
pdb10 2 0 0 3 FB1_4 STD 4 I/O O
(unused) 0 0 0 5 FB1_5 6 GCK/I/O
(unused) 0 0 0 5 FB1_6 8 I/O
(unused) 0 0 0 5 FB1_7 7 GCK/I/O
pdb13 2 0 0 3 FB1_8 STD 9 I/O O
(unused) 0 0 0 5 FB1_9 11 I/O
(unused) 0 0 0 5 FB1_10 12 I/O
(unused) 0 0 0 5 FB1_11 13 I/O
pdb15 1 0 0 4 FB1_12 STD 14 I/O O
tdo 1 0 0 4 FB1_13 STD 18 I/O I/O
(unused) 0 0 0 5 FB1_14 19 I/O
(unused) 0 0 0 5 FB1_15 20 I/O
(unused) 0 0 0 5 FB1_16 22 I/O
pdb11 3 0 0 2 FB1_17 STD 24 I/O O
N270/N270_TRST 4 0 0 1 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: tdo.PIN 5: pdb14 9: s1
2: ispen.PIN 6: s2 10: pdb8
3: pdb6 7: pdb5 11: pdb7
4: pdb9 8: s0
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
pdb12 ...X.X.XXX.............................. 5 5
pdb10 X....X.XX.X............................. 5 5
pdb13 XX...X.XX............................... 5 5
pdb15 .....X.X................................ 2 2
tdo ..X..X.XX............................... 4 4
pdb11 X.X..X.XXX.............................. 6 6
N270/N270_TRST ....XXXXX............................... 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 9/45
Number of signals used by logic mapping into function block: 9
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 1 I/O I
tdi 5 0 0 0 FB2_2 STD 44 I/O O
(unused) 0 0 0 5 FB2_3 42 GTS/I/O
(unused) 0 0 0 5 FB2_4 43 I/O I
(unused) 0 0 0 5 FB2_5 40 GTS/I/O I
(unused) 0 0 0 5 FB2_6 39 GSR/I/O I
tms 5 0 0 0 FB2_7 STD 38 I/O O
(unused) 0 0 0 5 FB2_8 37 I/O I
(unused) 0 0 0 5 FB2_9 36 I/O I
(unused) 0 0 0 5 FB2_10 35 I/O I
tck 4 0 0 1 FB2_11 STD 34 I/O O
(unused) 0 0 0 5 FB2_12 33 I/O I
(unused) 0 0 0 5 FB2_13 29 I/O I
(unused) 0 0 0 5 FB2_14 28 I/O I
ispen 3 0 0 2 FB2_15 STD 27 I/O I/O
(unused) 0 0 0 5 FB2_16 26 I/O I
(unused) 0 0 0 5 FB2_17 25 I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: "N270/N270_TRST" 4: s0 7: pdb3
2: s2 5: s1 8: pdb2
3: pdb5 6: pdb8 9: pdb4
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
tdi XX.XXXXX................................ 7 7
tms XX.XX.X.X............................... 6 6
tck XX.XX.XX................................ 6 6
ispen .XXXX................................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
pdb10 = /s0 * /s1 * tdo.PIN
+ s0 * /s2 * s1 * pdb7
pdb11 = s0 * /s2 * tdo.PIN
+ pdb6 * /s0 * s2 * /s1
+ /s0 * /s2 * s1 * pdb8
pdb12 = /s0 * s2 * /s1
+ /s0 * /s2 * pdb8
+ s0 * /s2 * s1 * pdb9
pdb13 = s0 * /s2 * s1 * ispen.PIN
+ /s0 * /s2 * s1 * tdo.PIN
pdb15 = /s0 * /s2
tck = s0 * /s2 * pdb2
+ /s0 * /s2 * pdb3
+ /s0 * s2 * /s1 * pdb2
tck.TRST = "N270/N270_TRST"
tdi = /s0 * /s2 * pdb2
+ s0 * /s2 * s1 * pdb8
+ s0 * /s2 * /s1 * pdb3
+ /s0 * s2 * /s1 * pdb3
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