📄 s_machine.vhd
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library IEEE;
use IEEE.std_logic_1164.all;
entity s_machine is --使mux51a从5个循环增加到8个循环
port
(
sin : in std_logic_vector(2 downto 0);
state : in std_logic_vector(2 downto 0);
sout : out std_logic_vector(2 downto 0)
);
end s_machine;
architecture bhav of s_machine is
begin
process(state,sin)
begin
if sin < "101" then sout <= sin;
else sout <= state;
end if;
end process;
end bhav;
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