hello.vhd

来自「DE2板上的hello程序,实现在8个七段译码器上循环显示hello」· VHDL 代码 · 共 69 行

library IEEE;
use IEEE.std_logic_1164.all;


entity Hello is             --3个器件的总体连接
	port
		(   SW : in  std_logic_vector(17 downto 0);
		  HEX0 : out std_logic_vector(0 to 6);
		  HEX1 : out std_logic_vector(0 to 6);
		  HEX2 : out std_logic_vector(0 to 6);
		  HEX3 : out std_logic_vector(0 to 6);

		  HEX4 : out std_logic_vector(0 to 6);
		  HEX5 : out std_logic_vector(0 to 6);
		  HEX6 : out std_logic_vector(0 to 6);
		  HEX7 : out std_logic_vector(0 to 6)
		);
end Hello;

architecture bhav of Hello is

	component mux51a
		port
		(              
		                 s : in  std_logic_vector(2 downto 0);
		 u , v , w , x , y : in  std_logic_vector(2 downto 0);
						 m : out std_logic_vector(2 downto 0)
		);
	end component;
	
	component s_machine
		port
		(
			  sin : in  std_logic_vector(2 downto 0);
			 sout : out std_logic_vector(2 downto 0)
		);
	end component;
	
	component char_87seg
		port
		(     
		      CIN : in  std_logic_vector(2 downto 0);
		 DISPLAY0 : out std_logic_vector(0 to 6);
		 DISPLAY1 : out std_logic_vector(0 to 6);  
		 DISPLAY2 : out std_logic_vector(0 to 6);
		 DISPLAY3 : out std_logic_vector(0 to 6);
		 DISPLAY4 : out std_logic_vector(0 to 6);
		 DISPLAY5 : out std_logic_vector(0 to 6);
		 DISPLAY6 : out std_logic_vector(0 to 6);
		 DISPLAY7 : out std_logic_vector(0 to 6)
		);
	end component;
	
	signal R : std_logic_vector(2 downto 0);
	signal T : std_logic_vector(2 downto 0);
	
	begin
--		T0 : s_machine port map(sin=>S , cout=>SW(17 downto 15));
		M0 : mux51a port map(s=>SW(17 downto 15) , u=>SW(14 downto 12) , 
							 v=>SW(11 downto 9 ) , w=>SW(8 downto 6) , 
							 x=>SW( 5 downto 3 ) , y=>SW(2 downto 0) , 
							 m=>R );
							
--		S0 : s_machine port map(sin=>R , sout=>T);
		
		H0 : char_87seg port map(CIN=>R , DISPLAY0=>HEX7 , DISPLAY1=>HEX6 , 
								 DISPLAY2=>HEX5 , DISPLAY3=>HEX4 , DISPLAY4=>HEX3 , 
								 DISPLAY5=>HEX2 , DISPLAY6=>HEX1 , DISPLAY7=>HEX0);
end bhav;