mux21a.vhd

来自「DE2板上的hello程序,实现在8个七段译码器上循环显示hello」· VHDL 代码 · 共 17 行

library IEEE;
use IEEE.std_logic_1164.all;

entity mux21a is                  --1bit的2选1多路选择器  s=0 时输出 x
	port 
		(
			x , y :  in  std_logic;
			    s :  in  std_logic;
			    m :  out std_logic
		);
end;


architecture bhav of mux21a is
	begin
		m <= x when s = '0'  else y;
end architecture bhav;