mux21b.vhd

来自「DE2板上的hello程序,实现在8个七段译码器上循环显示hello」· VHDL 代码 · 共 32 行

library IEEE;
use IEEE.std_logic_1164.all;

entity mux21b is                       --3bit输入的2选1 S=0 时输出 X
	port
		( X , Y : in  std_logic_vector(2 downto 0);
			  S : in  std_logic;
			  M : out std_logic_vector(2 downto 0)
		);
end;

architecture bhav of mux21b is
	component mux21a
		port 
		(
			x , y :  in  std_logic;
			    s :  in  std_logic;
			    m :  out std_logic
		);
	end component;
	
	
	begin
		u1 : mux21a port map(x=>X(0) , y=>Y(0) , s=>S , m=>M(0));
		u2 : mux21a port map(x=>X(1) , y=>Y(1) , s=>S , m=>M(1));
		u3 : mux21a port map(x=>X(2) , y=>Y(2) , s=>S , m=>M(2));
--		u4 : mux21a port map(x=>X(3) , y=>Y(3) , s=>S , m=>M(3));
--		u5 : mux21a port map(x=>X(4) , y=>Y(4) , s=>S , m=>M(4));
--		u6 : mux21a port map(x=>X(5) , y=>Y(5) , s=>S , m=>M(5));
--		u7 : mux21a port map(x=>X(6) , y=>Y(6) , s=>S , m=>M(6));
--		u8 : mux21a port map(x=>X(7) , y=>Y(7) , s=>S , m=>M(7));
end architecture bhav;