hello.tan.rpt

来自「DE2板上的hello程序,实现在8个七段译码器上循环显示hello」· RPT 代码 · 共 304 行 · 第 1/3 页

Timing Analyzer report for Hello
Mon Jun 25 14:12:11 2007
Version 6.0 Build 178 04/27/2006 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                      ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From   ; To      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 18.112 ns   ; SW[16] ; HEX7[0] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;        ;         ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; tpd                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+-----------------+--------+---------+
; Slack                                   ; Required P2P Time                                   ; Actual P2P Time ; From   ; To      ;
+-----------------------------------------+-----------------------------------------------------+-----------------+--------+---------+
; N/A                                     ; None                                                ; 18.112 ns       ; SW[16] ; HEX7[0] ;
; N/A                                     ; None                                                ; 18.083 ns       ; SW[15] ; HEX7[0] ;
; N/A                                     ; None                                                ; 17.752 ns       ; SW[14] ; HEX7[0] ;
; N/A                                     ; None                                                ; 17.724 ns       ; SW[13] ; HEX7[0] ;
; N/A                                     ; None                                                ; 17.629 ns       ; SW[16] ; HEX5[3] ;
; N/A                                     ; None                                                ; 17.603 ns       ; SW[16] ; HEX4[6] ;
; N/A                                     ; None                                                ; 17.600 ns       ; SW[15] ; HEX5[3] ;
; N/A                                     ; None                                                ; 17.574 ns       ; SW[15] ; HEX4[6] ;
; N/A                                     ; None                                                ; 17.551 ns       ; SW[16] ; HEX3[3] ;
; N/A                                     ; None                                                ; 17.522 ns       ; SW[15] ; HEX3[3] ;
; N/A                                     ; None                                                ; 17.511 ns       ; SW[16] ; HEX1[3] ;
; N/A                                     ; None                                                ; 17.482 ns       ; SW[15] ; HEX1[3] ;
; N/A                                     ; None                                                ; 17.357 ns       ; SW[16] ; HEX7[3] ;
; N/A                                     ; None                                                ; 17.328 ns       ; SW[15] ; HEX7[3] ;
; N/A                                     ; None                                                ; 17.312 ns       ; SW[16] ; HEX4[4] ;
; N/A                                     ; None                                                ; 17.312 ns       ; SW[16] ; HEX4[5] ;
; N/A                                     ; None                                                ; 17.294 ns       ; SW[16] ; HEX2[4] ;
; N/A                                     ; None                                                ; 17.294 ns       ; SW[16] ; HEX2[5] ;
; N/A                                     ; None                                                ; 17.285 ns       ; SW[16] ; HEX2[6] ;
; N/A                                     ; None                                                ; 17.283 ns       ; SW[15] ; HEX4[4] ;
; N/A                                     ; None                                                ; 17.283 ns       ; SW[15] ; HEX4[5] ;
; N/A                                     ; None                                                ; 17.269 ns       ; SW[14] ; HEX5[3] ;
; N/A                                     ; None                                                ; 17.265 ns       ; SW[15] ; HEX2[4] ;
; N/A                                     ; None                                                ; 17.265 ns       ; SW[15] ; HEX2[5] ;
; N/A                                     ; None                                                ; 17.256 ns       ; SW[15] ; HEX2[6] ;
; N/A                                     ; None                                                ; 17.254 ns       ; SW[16] ; HEX4[0] ;