hello.map.rpt

DE2板上的hello程序,实现在8个七段译码器上循环显示hello

+----------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                      ;
+---------------------------------------------+------------------------------------+
; Resource                                    ; Usage                              ;
+---------------------------------------------+------------------------------------+
; Estimated Total logic elements              ; 45                                 ;
; Total combinational functions               ; 45                                 ;
; Logic element usage by number of LUT inputs ;                                    ;
;     -- 4 input functions                    ; 10                                 ;
;     -- 3 input functions                    ; 25                                 ;
;     -- <=2 input functions                  ; 10                                 ;
;         -- Combinational cells for routing  ; 0                                  ;
; Logic elements by mode                      ;                                    ;
;     -- normal mode                          ; 45                                 ;
;     -- arithmetic mode                      ; 0                                  ;
; Total registers                             ; 0                                  ;
; I/O pins                                    ; 74                                 ;
; Maximum fan-out node                        ; mux51a:M0|s_machine:u5|sout[1]~245 ;
; Maximum fan-out                             ; 31                                 ;
; Total fan-out                               ; 191                                ;
; Average fan-out                             ; 1.61                               ;
+---------------------------------------------+------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                  ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                  ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------------------------------+
; |Hello                     ; 45 (0)            ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 74   ; 0            ; |Hello                               ;
;    |char_87seg:H0|         ; 32 (0)            ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0                 ;
;       |char_7seg:SEG1|     ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0|char_7seg:SEG1  ;
;       |char_7seg:SEG2|     ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0|char_7seg:SEG2  ;
;       |char_7seg:SEG3|     ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0|char_7seg:SEG3  ;
;       |char_7seg:SEG4|     ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0|char_7seg:SEG4  ;
;       |char_7seg:SEG5|     ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0|char_7seg:SEG5  ;
;       |char_7seg:SEG6|     ; 4 (4)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0|char_7seg:SEG6  ;
;       |char_7seg:SEG7|     ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0|char_7seg:SEG7  ;
;       |char_7seg:SEG8|     ; 4 (4)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0|char_7seg:SEG8  ;
;       |cnt8:ADD4|          ; 1 (1)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0|cnt8:ADD4       ;
;       |cnt8:ADD5|          ; 2 (2)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0|cnt8:ADD5       ;
;       |cnt8:ADD6|          ; 2 (2)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0|cnt8:ADD6       ;
;       |cnt8:ADD7|          ; 1 (1)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|char_87seg:H0|cnt8:ADD7       ;
;    |mux51a:M0|             ; 13 (0)            ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|mux51a:M0                     ;
;       |mux21b:u4|          ; 10 (0)            ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|mux51a:M0|mux21b:u4           ;
;          |mux21a:u1|       ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|mux51a:M0|mux21b:u4|mux21a:u1 ;
;          |mux21a:u2|       ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|mux51a:M0|mux21b:u4|mux21a:u2 ;
;          |mux21a:u3|       ; 4 (4)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|mux51a:M0|mux21b:u4|mux21a:u3 ;
;       |s_machine:u5|       ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |Hello|mux51a:M0|s_machine:u5        ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; 5:1                ; 3 bits    ; 9 LEs         ; 9 LEs                ; 0 LEs                  ; No         ; |Hello|mux51a:M0|mux21b:u4|mux21a:u1|m ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Mon Jun 25 14:11:19 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Hello -c Hello
Info: Found 2 design units, including 1 entities, in source file mux21a.vhd
    Info: Found design unit 1: mux21a-bhav
    Info: Found entity 1: mux21a
Info: Found 2 design units, including 1 entities, in source file mux51a.vhd
    Info: Found design unit 1: mux51a-bhav
    Info: Found entity 1: mux51a
Info: Found 2 design units, including 1 entities, in source file mux21b.vhd
    Info: Found design unit 1: mux21b-bhav
    Info: Found entity 1: mux21b
Warning: Can't analyze file -- file D:/altera/程序/Hello/bin27seg.vhd is missing
Info: Found 2 design units, including 1 entities, in source file Hello.vhd
    Info: Found design unit 1: Hello-bhav
    Info: Found entity 1: Hello
Warning: Can't analyze file -- file D:/altera/程序/Hello/cnt3.vhd is missing
Warning: Can't analyze file -- file D:/altera/程序/Hello/clkmux51.vhd is missing
Info: Found 2 design units, including 1 entities, in source file cnt8.vhd
    Info: Found design unit 1: cnt8-bhav
    Info: Found entity 1: cnt8
Info: Found 2 design units, including 1 entities, in source file char_87seg.vhd
    Info: Found design unit 1: char_87seg-bhav
    Info: Found entity 1: char_87seg
Info: Found 2 design units, including 1 entities, in source file s_machine.vhd
    Info: Found design unit 1: s_machine-bhav
    Info: Found entity 1: s_machine
Info: Found 2 design units, including 1 entities, in source file char_7seg.vhd
    Info: Found design unit 1: char_7seg-bhav
    Info: Found entity 1: char_7seg
Info: Elaborating entity "Hello" for the top level hierarchy
Info: Elaborating entity "mux51a" for hierarchy "mux51a:M0"
Info: Elaborating entity "mux21b" for hierarchy "mux51a:M0|mux21b:u1"
Info: Elaborating entity "mux21a" for hierarchy "mux51a:M0|mux21b:u1|mux21a:u1"
Info: Elaborating entity "s_machine" for hierarchy "mux51a:M0|s_machine:u5"
Info: Elaborating entity "char_87seg" for hierarchy "char_87seg:H0"
Info: Elaborating entity "cnt8" for hierarchy "char_87seg:H0|cnt8:ADD0"
Warning (10492): VHDL Process Statement warning at cnt8.vhd(34): signal "cqi" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "char_7seg" for hierarchy "char_87seg:H0|char_7seg:SEG1"
Info: Implemented 119 device resources after synthesis - the final resource count might be different
    Info: Implemented 18 input pins
    Info: Implemented 56 output pins
    Info: Implemented 45 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Mon Jun 25 14:11:29 2007
    Info: Elapsed time: 00:00:10