ram_basic.ncf

《设计与验证Verilog HDL》光盘内容

#
# Constraints generated by Synplify Pro 8.1.0, Build 540R
#

# Period Constraints

#Begin clock constraints
NET "clk" TNM_NET = "clk"; 
TIMESPEC "TS_clk" = PERIOD "clk" 2.717 ns HIGH 50.00%; 
#End clock constraints

# Output Constraints
# Input Constraints

# I/O Registers Packing Constraints
INST "mem_data[6]" IOB=FALSE;
INST "mem_data[5]" IOB=FALSE;
INST "mem_data[4]" IOB=FALSE;
INST "mem_data[3]" IOB=FALSE;
INST "mem_data[2]" IOB=FALSE;
INST "mem_data[1]" IOB=FALSE;
INST "mem_data[0]" IOB=FALSE;

# Location Constraints

# End of generated constraints